Study On Hot Carrier Effects Of Nanometer Small Size MOSFETs

Reliability issues have been always accompanying with the development and application of VLSI. With the scaling-down of metal-oxide-semiconductor field effect transistor (MOSFET), the new physical mechanism is found in hot carrier injection (HCI) effect and has seriously affected the life of the device. HCI degradation has been one of the very important reliability problems on nanometer small-size device. Nanometer small size (0.13μm-32nm) devices prepared by the standard CMOS IC technology have been used in this article. Combined with the current status of theoretical models and research base of our group, we have studied the worst HCI stress condition for each process node, major degradation mechanism for HCI, Characterization of defects induced by HCI degradation and variability of device parameters caused by HCI degradation. The main results are as follows:(1) We have studied HCI degradation worst stress conditions for nMOSFET and pMOSFET devices at the various technology nodes (0.35μm-45nm). It is found that as technologies nodes shrink, the HCI degradation worst stress conditions from the gate voltage at the maximum substrate current (Vgs@Ibmax) and low temperature are converted into the gate voltage which is equal to drain voltage (Vgs=Vds) and high temperature. Under the worst stress condition, the HCI degradations at different stress voltage are tested for each technology node. It is found that for nanometer small size nMOSFET, the positive bias temperature instability (PBTI) degradation occurs with increasing of stress conditions (voltage or temperature). HCI degradation stress conditions excluding PBTI degradation are obtained by experiments.(2) For nanometer nMOSFET, the HCI degradation mechanism becomes more complicated with scaling-down. Under the worst stress conditions, HCI degradation is measured for the different gate length (from0.12μm to32nm) nMOSFET. It is found that HCI degradation characteristics are different for devices with different gate length. Utilizing the surface potential characterization technique, we study distribution along the channel of threshold voltage shift (△VT) induced by HCI degradation. It is found that the proportion of HCI degradation induced△VT distribution range to gate length is increased as gate channel shrink. The temperature effect of△VT at different channel positions is analyzed and two HCI degradation mechanisms, including channel hot electron mechanism and electron-electron scatter mechanism.It is found from experiments that channel hot electron is the main degradation mechanism for long channel length devices (L≥0.12um). Electron-electron scatter is the main degradation mechanism for short channel length devices. For nanometer devices with gate length between0.12um-32nm, channel hot electron injection and electron-electron scatter exist simultaneously. The results analysis showed that the range of channel hot electron mainly in the area near the drain, while the range of electron-electron scatter extended to the source. With the increasing of gate length, the range of channel hot electron decrease and the range of electron-electron scatter increase.(3) We study the variability of device parameters induced by HCI for MOSFET with different gate length (from0.4μm to40nm) and gate width (from1Oμm to1μm). It is found that the variability of device parameters after HCI degradation becomes more serious with scaling-down of devices. We analyze the main source variability of device parameters after HCI degradation. The key factors are analyzed which effect the variability of device parameters. A prediction model of the variability of device parameters induced by HCI degradation is proposed and the physical significance of this model is analyzed in detail.(4) As scaling-down, the proportion of the source-drain series resistance has been increasing, which severely limiting the driving capability of the device. Accurate extracting source-drain series resistance and examining its behavior is a critical issue for deeply scaled MOSFETs. We study various methods of extracting the source and drain series resistance and select four methods with smaller error for comparing, including the constant-mobility method, the direct Id-Vgs method, the Y-function method and the conductance method. We extract the source-drain series resistance and study their respective gate length dependence. It is found that achieved source-drain series resistance from the constant-mobility method exhibits the channel length independent characteristics, however, gate length-dependent source-drain series resistances are extracted from the other three methods. We have analyzed the error of each method and the constant-mobility method is proven to extract the most accurate source and drain series resistance values. According to the theoretical analysis and experimental research, a new method is proposed for accurate source-drain series resistance extraction on nanometer small scaled MOSFETs. The application of this method is simple and the values extracted exclude the effects of various errors, which is accurate.