Design And Implementation Of Digital Unit For High Speed Direct Digital Frequency Synthesizer

Direct Digital Frequency Synthesizer(DDS)as a new all-digital synthesis device with higher frequency resolution,shorter frequency switching time,lower phase noise and many other advantages than analog frequency synthesizer plays an important role in electronic systems such as space communication,telemetry and remote control,radar measurement,radio astronomy,satellite navigation,radio positioning,and digital communication.In recent years,with the development of semiconductor process technology and integrated circuit(IC)technology,small size,low power consumption and high integration are the inevitable trends of chip development.Therefore,the current research hotspots of DDS systems are also developing towards ultra-high speed,low power consumption and high performance.The paper relies on the“High-speed Multi-channel DDS Design”project and completes the design of“Digital Unit Design and Implementation of High-Speed Direct Digital Synthesizer with multi-channel”.In order to realize the design and implementation of high-speed DDS digital unit,this paper is mainly divided into the three parts.The first part mainly analyzes the key module in the DDS architecture—the phase-to-amplitude conversion module.By comparing the advantages and disadvantages of the four common phase-conversion algorithms,the improved CORDIC algorithm(the Excess-four algorithm)is selected as the DDS phase-amplitude conversion algorithm.Then use Matlab software to simulate the Excess-four algorithm to ensure the correctness of the Yusi algorithm,which lays a solid foundation for hardware implementation.In addition,we deeply analyze the principle and framework of DDS to analyze the sources of spurs generated by DDS and the current spurious suppression method is introduced.The second part lays the foundation for the circuit realization through the pre-algorithm simulation,and completes the design work of the digital front-end register transfer level(RTL)code.In the circuit design process,in order to save The consumption of hardware resources,the circuit structure is optimized in circuit implementation,and in order to enable the DDS system to achieve a higher Spurious-Free Dynamic Range(SFDR)performance,The phase scrambling code design and the spurious cancellation design are performed.The behavioral level verification of the designed RTL code is carried out by Modelsim software to test the circuit design through the laboratory hardware resources,and the correctness of the circuit design is verified.The third part is mainly the digital circuit back-end design.Based on the ASIC design flow,the TSMC 65nm CMOS process is used to perform logic synthesis,formal verification and layout implementation of the RTL code of the front-end design,and finally complete the design of the digital unit of the high-speed single-channel DDS system.The DDS system digital unit designed by the final project has a spurious-free dynamic range of less than-88dBc,which satisfies the design specifications,and its area is about 0.64mm~2,and the power consumption is 504.36mW.