Research On The Key Technology Of A High Efficiency And Ultra High-speed Direct Digital Frequency Synthesizer

DDS is constantly updated and optimized with the rapid development of the integrated circuit industry.Its role is becoming more and more important,as a hot research direction of current frequency generator.On the one hand,DDS has the advantages of high frequency resolution,fast phase conversion time,low noise and low power consumption.On the other hand,the bandwidth and stray of DDS are the most influential factors,so it is necessary to study the key technology of high performance and high speed DDS chips.This thesis first introduces the principle and basic structure of DDS,and describes each module and its functions in detail.After that,the performance index of DDS is analyzed,and the common three kinds of stray,such as phase accumulator,output and stray,amplitude value quantization and stray,and DAC transformation and stray are introduced.The methods to reduce stray and improve the performance of DDS are introduced,and the method is used in this design.In view of the phase amplitude conversion module of the core part of DDS,the principle and the advantages and disadvantages of the classical CORDIC algorithm are emphatically analyzed,and then a phase amplitude conversion algorithm is designed based on the classic CORDIC algorithm.The algorithm sets the bit width of the phase accumulator to 32-bit,and truncate the output data to 19-bit as the phase word,in which the high third bit of the phase word is selected as the eight partition for the final waveform synthesis,and the second 7 bits as the addressing address of the rough lookup table,which is used to index the initial amplitude value,and the last 9 bits are used as the fine tune.Addressable address for fine adjustment of coarse values.At the same time,the algorithm adopts sine linear phase bias difference method and cosine linear phase bias difference method to compress the amplitude value of the storage in the rough lookup table,then the amplitude value is reduced by the adder,and the amplitude value of the fine tune lookup table is also compressed to a certain extent,so that it is with the classical CORDIC algorithm.It not only speeds up the number of computation iterations,but also reduces the power consumption and memory resource occupancy of the hardware circuit,improves the running speed,and achieves high efficiency design requirements.On the other hand,the Dither pseudo random sequence generator is added,and the DDS is optimized by multi-channel interpolation structure and current steering DAC.The DDS of this thesis supports three modes of operation:single frequency output,linear scan output and Profile output,and can complete a variety of signal modulation outputs.FFT analysis of the output results,SFDR around 102dB,has reached the goal of high SFDR.Finally,in the SMIC 180nm 1P6M process,the DDS is designed by logical synthesis and physical realization.The logical synthesis time series report shows that the key path of DDS needs 3.57ns,the frequency is 200MHz.After the 16 channel is reorganized,the maximum frequency of the synthesized signal can reach 3.2GHz,which is in line with the ultra high speed requirement of the design.The area report shows that the DDS chip has38466 units,of which 21340 are combined logic,12138 time series logic,1022buffer/reverse units,and a total area of 13350053.051716?m~2.After layout and routing,the chip area is 1150×1725?m~2.The clock tree analysis shows that the insertion delay is 2ns,the clock tree is 7 levels,and the maximum value of clock deviation is 129ps.The power consumption report shows that the total power consumption is 526.75mW,of which the internal power consumption is 367.752mW,the switching power consumption is158.912mW,and the static power consumption is 0.09540mW.Finally,physical verification is carried out to ensure the correctness of the DDS chip.