Performance Optimization Of Semiconductor Chip Test Data Recording

With the rapid development of both domestic and overseas semiconductor industry,semiconductor chip test has gradually taken a more and more important position in chip manufacturing,for which those ATE companies are going in quest of cost reduction and high efficiency.Meanwhile,module test software and auxiliary software have played a great quantity of roles during practical application,usually the data stream of test platform gets analyzed,managed and packaged by computer test software the first time it produced,as the performance of test software is the key issue impacting the performance of the whole test process.So the scheme to solve problems accompanied by rise-number test data like data stream blocking,high IO occupancy,extortionate time cost indeed meets the need of semiconductor industry.The dissertation has carried out following research on performance optimization of test software:1.A state and an analysis of data types applied among semiconductor companies and their test schemes.Presenting a scheme utilizing compression algorithm and parallelization to improve the performance of data producing,converting and recording during the Advantest's process containing EDL file and STDF file.2.Test and compare different compression algorithm for a better adaption to characteristics of EDL,STDF files and practical application.And the Deflate algorithm(contained in zlib)and LZ4 algorithm are selected for the compression on the process of converting from EDL to STDF and data recording,since their convince and flexible code compiling adapt to data files' complicated structure.3.According to C++11 standard library and the optimized data recording process,analyze and design an appropriate parallelization scheme.Then extend the parallelization to cover the whole process from data producing as EDL file to ultimately data recording as the compression of STDF file.All above shall be complying with the requirement of STDF standard and file integrity.According to the characteristics of chip test software during process of chip test,this dissertation provides a scheme of compression and parallelization to optimize software's performance.The scheme has performed well in the company's practical engineering test environment when testing and comparing multiple actual chip test data.The minimum file compression rate is 15.7% and the maximum can exceed 60%.The average time consumption is shortened by nearly 30%.It can be seen the scheme has indeed improved software performance by optimizing the process of test data managing and recording.