Research And Implementation Of Successive Approximation ADC For Wireless Sensor Network Applications

With the fast development of CMOS technology, system on chip (SOC) design has become an important developing trend of the integrated circuit. A large number of IP cores have been integrated on a single chip, such as digital signal processor (DSP), data converter, filter, memory, et al. Digital signal processing is gradually taking the place of the traditional analog signal processing due to its high reliability, strong flexibility, and low cost. As physical signals such as force, heat, electricity, light, sound and temperature are all analog signals, analog-to-digital converter (ADC) is required which converts the analog signal into the digital signal.ADC is a fundamental block for wireless sensor networks (WSN). WSN contains multiple sensor nodes. In most cases, changing their batteries is impractical, therefore, low power design of the WSN has become an important research issue. Among different conversion topologies, Successive Approximation Register (SAR) ADC has been widely used for its simple structure, low power, small area and compatibility with standard digital CMOS technology. The main aim of this thesis is designing a low power10bit1MS/s SAR ADC which can work at0.6V supply voltage. The main contributions and innovation are as follows:1. The SAR ADC is mainly composed of digital to analog converter (DAC), comparator, and digital control logic, etc. In this thesis, a detailed analysis of the performance of these circuits in terms of accuracy, speed, and power consumption is presented, and then it is applied in the design of the SAR ADC.2. In the DAC, the Vcm-based switching schemes are not employed, due to the low supply voltage. In this thesis, monotonic switching scheme is employed in the DAC due to its power efficiency and simplified digital logic. While the main drawback of monotonic switching scheme is its large common mode shift and the associated comparator offset dynamic variation. The varying offset is the major source of integral nonlinearity (INL). To solve this problem, the conventional constant current biasing technique can’t be applied to the dynamic comparator due to the limited headroom. Another method uses a supply-boost technique to increase the supply voltage of the comparator to2×VDD, which allows constant current biasing but significantly increased the power consumption. Common mode stabilizer (CMS) is proposed for the first time to address this issue in low-voltage design. Simulation results show that with the proposed common mode stabilizer applied, the performance of the static and dynamic is greatly improved. The effectiveness of this method is also verified through the measurement results.3. In the comparator, a preamplifier with dynamic latch is adopted in this thesis. The offset voltage and kickback noise can both be reduced with the preamplifier applied. Therefore, the accuracy of the comparator can be improved. In order to reduce the power consumption, dynamic circuit is used. Furthermore, the speed of the comparator can be increased by using the regenerative latch.4. In the digital logic circuit, the asynchronous logic is adopted for the low power and high speed.5. In the switches with low voltage supply, boostrapping technique is used in the sampling switch which can increase the range of the input signal and improve the linearity of the sampling switch. While the boostrapping technique consumes large area and power consumption, top plate sampling technique is employed so that the number of switches which should treat the input signal ranging from supply voltage to ground is reduced to two. The power consumption of the switches is greatly reduced.6. This thesis details and calculates the power consumption of every building block in the SAR ADC, and summarizes a general design method about SAR ADC. The power consumption can be calculated under the accuracy and the speed requirement. Therefore, the size of the transistors in the SAR ADC can be chosen.A10-bit1MS/s SAR ADC is implemented based on TSMC0.13μm CMOS technology. The core area is only0.04mm2. This thesis also discusses the test of ADC, which is including static and dynamic parameter test. The measurement results show that the proposed SAR ADC consumes6.3μW at1MS/s from0.6V supply, and achieves51.25dB SNDR at Nyquist frequency and FOM of21fJ/conversion-step. The measured peak DNL and INL are-0.91/+1.58LSB and-1.15/+1.99LSB, respectively. The proposed SAR ADC meets the requirements of the WSN.