The Research On Failure Prediction And Tracking Monitor Technology Of Aging For Digital Integrated Circuit

With the development of semiconductor process technology, the rapid scaling of CMOS technology has accelerated the transistor degradation. Especially for Negative Bias Temperature Instability(NBTI), which can cause delay degradation in more than10%. Further experimental data indicates that NBTI worsens exponentially with thinner gate oxide and higher operating temperature. Considering improving the circuit reliability as the breakthrough point, in this dissertation, the technology of aging failure prediction and tracking degradation monitor has been studied, the main work are shown as follows:To begin with, the concepts of aging prediction and online detection are studied, as well as the research achievements in these fields in recent years. The general principles of aging caused by NBTI are introduced in detail, the existing solutions are classified, and the advantages and disadvantages of each method are analyzed and compared.What’s more, to reduce the paths of aging prediction, an iterative algorithm based on types and number of logic gates on one path is proposed. In this algorithm, all paths are classified into three factors according to the number of each logic gate types and their influence on circuit aging:the critical path, which affects the performance of circuit; the potential critical path, which may be affected by aging; and the protected path, which can not have influence on the circuit. Then removing the secure path which will not occur aging, lessening the workload of circuit aging prediction, and improving the efficiency of aging prediction. The experimental data indicates that, the algorithm has a high effect on the majority of the integrated circuits, and can reduce average paths of ICs in 40%.Finally, a self-latching ring oscillator aging monitor design for measure the aging level is introduced in this paper. The design uses the inverters in ring oscillator, AT-CELL consists of this inverter and another reverse inverter. AT-CELL can detect the location of input signal edge in the ring oscillator. AT-CELL uses the architecture features of three state gate, there are two operating modes:ososcillation status and test status. Experimental results demonstrate that this structure is designed to be simple and accurate, the measured result of this aging monitor shows that the experimental precision is more than 90%. compared with other traditional solutions, it can save more than half of area, therefore this structure has a high practical value.