Structure Design、Modeling And Simulation Of Novel MOSFET

For the past few decades, the size of the device has decreased continuously, following the principle of scaling-down. With the feature size of MOSFET device decreasing into sub 100nm even nano level, a great many technical parameter of the device is approaching its physical limit. As the device channel length decreases gradully, the proportion of the source and drain depletion region becomes larger and larger. The device performance, has very large deviation from long channel device performance, because of the two-dimension potential and strong electric field in short channel. The electric charge in the channel becomes less and less, causing the threshold voltage decreases, which in the end get out of control. That is the short channel effect. When the channel is very short, with the drain voltage increases, the source is influenced by the electric field of drain. The barrier of source decreases under the influence of the electric field and then more and more electron go into the channel from the source, which cause the increase of the drain curren. That is drain induced barrier lowering effect. For a given drain voltage, the smaller the device size is, the more significantly drain current increases, and then finally the device cannot be turned off and can’t work normally. When the length reduce to a certain extent, electric field in the device is very strong, especially around the source/drain. Hence, the carrier gets enough energy and becomes hot carrier. It affects the device in two aspects. First, the hot carriers pass through Si/SiO2 barrier and inject into the oxide layer. With the continuous accumulation, the threshold voltage is changed and the life of device is shortened. Secondly, the hot carriers bump into lattice in the depletion near the drain, which generates electron hole pair. For the NMOS, the electrons become the drain current, while the holes are collected by substrate as substrate current. According to the scaling-down law, the gate oxide thickness becomes thinner and thinner as MOSFET size decreases.1.2nm thickness gate oxide has been made in mainstream semiconductor technology, which equal to thickness five atoms overlay. With such size, some of the electrons have the opportunity getting through gate oxide and then generate gate leakage current. That is tunneling effect. To solve the above problems, the aspects of device technology, material and structure should be considered. The main work of this paper includes:(1) The overview of MOSFET research and modeling theory basis. The development, problems and trend of the integrated circuit is introduced in Chapter 1. Based on this, the research significance and the research content of this paper is put forward. Chapter 2 introduces the analytical model theory basis summarizing three modeling method of surface potential.(2) Gate of dual-material gate MOSFET constitutes of two different kinds of materials, thus a step electric potential in the channel is created. Near the interface of two kinds of materials, there is a peak electric field. Then the average electron velocity in the channel is increased which resulting in higher carrier drift velocity and device speed. The peak electric field at the drain is smaller than that of single material gate MOSFET which decreases the hot carrier effect at the same time. Moreover, the region near the source is screened from drain voltage variation, hence the effect of channel length modulation is suppressed. The single material dual workfunction gate MOSFET is presented in Chapter 3, inspired by the DMG MOSFET. The gate near source is P-type doping while the gate near the drain is N-type doping, because the work function of P-type doping is higher than that of N-type doping. The analytical potential model is established based on parabola method. The device simulator MEDICI is used to test the model. The results show that the analytical model is in good agreement with MEDICI simulation curve. Finally, the various characteristics of the device are analyzed.(3) In the lightly doped drain MOSFET, there is a lightly doped region close to the source/drain in the channel. This region can withstand part of voltage, reduce electric field near the drain and prevent hot electron degradation effect. The single material dual workfunction gate lightly doped drain MOSFET is presented in Chapter 4, based on Chapter 3. First, the gate manufacturing process is simulated by the process simulation software TSUPREM. Second, the analytical potential model is established based on parabola method. The model is simulated and verified by MEDICI. The results show that the analytical model is consistent with MEDICI. Finally, the various characteristics of the device are analyzed.(4) According to international technology roadmap for semiconductors in 2013, the mainstream technology of the device’s physical gate length will be reduced to 15nm in 2017. The corresponding gate oxide thickness will be reduced under 0.6nm. If the silicon dioxide is still used as gate dielectric, the electron tunneling effect will be very serious. Using high-k dielectric material has been proved one of the effective methods to overcome this problem. But the stability of the device is influenced by the interface layer between high-k dielectric and silicon. Gate stack dielectric dual-material gate fully depleted SOI MOSFET is presented in Chapter 5. The analytical potential model is established based on parabola method. The model is simulated and verified by MEDICI. The results show that the analytical model is consistent with MEDICI.