Threshold Voltage Model Of Small MOSFET And Preparation Of High-k Gate Dielectric

With aggressive reduction of characteristic length of MOSFET, some new physical phenomena, e.g. increase of gate leakage current, short channel effect etc., continuously occur. Increase of gate leakage leads to increase of static power dissipation, even the device being out of operation. The threshold voltage roll-off is enlarged due to enhancement of the short channel effect. To decrease gate leakage current, it is a feasible method that the suitable high-k material is employed as gate dielectric replacement of SiO2. However, when physical thickness of the gate dielectric is close to the channel length of MOSFET, influence of the fringing field effect on the threshold voltage becomes more and more severe besides short-channel effect and drain-induced barrier lowing effect. Aiming at the above problems, theoritical and experiment work involving the threshold voltage model of small MOSFET with high-k gate dielectric and preparation of high-k gate dielectric of MOS devices is respectively performed to find relevant solutions in this thesis. Theoritically, the threshold voltage models considering the above effects are built. Experimentally, preparation of HfTiON gate dielectric and influence of stack gate dielectric on electrical characteristics of MOS devices are mainly investigated.Firstly, the threshold voltage model including drain-induced barrier-lowering effect and short-channel effect is obtained through solving 2-D poisson equation by variation method. Influences of the drain-source voltage (Vds), gate dielectric constant and channel length on the threshold voltage are discussed in detail. The simulated results show that the threshold voltage is decreased with increasing of Vds and gate dielectric constant and shrinking of the channel length. To more accurately consider influence of fringing-field effect on the electrical characteristics MOS devices, the fringing capacitance model of small MOSFET with high-k gate dielectric is built by using conform mapping method. The simulated results show a good agreement with the results from Medici simulator. Based on this, the analytical distribution of fringing potential of the high-k gate dielectric is derived, and the threshold voltage model is modified using the fringing potential as boundary condition. The threshold voltage of MOSFET with different sidewall spacers is simulated, and it is found that the threshold voltage roll-off can be alleviated by using low-k sidewall spacer, thus obtaining the relevant theoretical supporting. Therefore, a low-k sidewall spacer should be used to alleviate the fringing-field effect.Experimentally, taking HfTiO gate dielectric as an example, influences of surface pretreatment on electrical characteristics of high-k gate dielectric MOS devices are first investigated. Then, preparaing technologies of HfTiON gate dielectric by co-sputtering of Hf and Ti targets in an ambient with/without O2 are investigated: (1) in O2 ambient, HfTiO gate dielectric films are deposited by O2-reactive co-sputtering of Hf and Ti targets. Then, HfTiO films are annealed in different natridation ambients, and transformed into HfTiON dielectric. Through comparing different samples, it is found that the NO annealed sample shows good interface properties, low gate leakage current and high reliability due to formation of a HfTiON/HfTiSiON stack gate dielectric; (2) HfTiN dielectric films are deposited though N2-reactive co-sputtering of Hf and Ti targets in an ambient without O2. Then, post-deposition annealing (PDA) is performed in N2 ambient at 700℃for 30 sec to oxide HfTiN into HfTiON by consuming residual oxygen in N2 and PDA system. Through comparing the two processes, the HfTiON gate dielectric fabricated in an ambient without O2 has higher k value than those samples fabricated in O2 ambient.To overcome poor thermal stability of Ti on Si surface, a stack gate dielectric structure with a thin interlayer including no Ti is designed and prepared: (a) before the HfTiN is deposited, SiON interlayer is thermally grown. Then , annealing in N2 forms the HfTiON/SiON stack gate dielectric. The results show that the NO pre-treated sample exhibits good electrical performances because its suitable nitridation/oxidation role and formation of a stoichiometry SiON interlayer; (b) to further increase equivalent k value of gate dielectric, a stack gate dielectric of HfTiON/HfSiON with HfSiON as interlayer is designed and fabricated. Compared to MOS device without HfSiON interlayer, the sample with HfTiON/HfSiON stack gate dielectric shows low interface state density, low gate leakage current and high reliability. In summary, the interfacal properties, gate leakage properties and reliability of MOS devices can effectively be improved by employing the two stack gate dielectric structures and corresponding preparing technologies. Undoubtedly, they are potential technologies to prepare high-quality small MOSFET with high-k materials as gate dielectric.