Embedded Image Recording Technology Based On NAND Flash

The NAND Flash has versatile features such as low-power consumption, excellenttemperature tolerance ability, non-volatility, high random access performance,solid-state reliability, shock resistance, and high mobility. It is suitable for designinghigh-speed image recorder system used in extreme environment. In this paper, to solvethe various problems involved in designing NAND Flash-based image recording system,architectures and algorithms that are more suitable for engineering applications andhave better performance are proposed.For how to improve the access speed of the NAND Flash, this paper studies theinternal structure and working principle of the NAND Flash, analysis the drive timingof various operations and realizes the various drive timing of NAND Flash’s operationsin the FPGA respectively. This paper researchs traditional pipelining and paralleltechnologies theoretically, finally, proposes an new method based on NAND flashon-chip interleave write and off-chip2level pipelining. Through the various controltechniques implemented in FPGA, it is demonstrated that the method presented has thelargest pipelining speedup, can effectively improve the writing speed while reducing theFPGA pin occupancy.In order to solve the problem of invalid block table’s fast search and reliable store,an invalid block information fast search architecture based on bit index is proposed. Aninvalid block pre-matching mechanism based on glide window is proposed to solve theproblem of invalid block’s fast matching. In consideration of the disadvantage thatburst invalid block will decrease write speed, this paper presents a lag copy backmechanism. Architecture is implemented in form of hardware. Moreover, efficientwear-leveling method suitable for sequence recording system is proposed andimplemented. At the same time, this paper proposes and implements a IO transformmethod, which can effectively avoid the NAND Flash recording system to use more ofthe NAND Flash controller, greatly saving FPGA internal resources.The problem of how to facilitate efficient task management for high-speed image recording is researched. Then, high-speed image memory caching mechanism isdesigned. This paper realizes the high-speed image data cache and additionalinformation embedding real-timely, presents a two-stage data indexing mechanism, andexpounds the mapping of task management in detail. To ensure the security of recordingdata, the task management related tables backup and update in NOR Flash. The practiceshows that these mechanisms can reduce the CPU cost, shorten the query time of taskinformation and image data, and is suitable for application in embedded system.In order to determine the elementary reliability of the recorder and the peakrecording speed, new load test models are designed. To solve the problem of stabilitytest, speed load model based on exponential regression and test time control modelbased on the lognormal distribution are proposed; to test the peak recording speed, thispaper presents the test methods combining hardware with software based on climbingsearch algorithm and speed dichotomy. These methods are implemented in the FPGA,the effectiveness of the proposed methods is verified.In order to promote practical engineering application of the relevant researchresults, this paper proposes and realizes the photoelectric theodolite NAND Flashembedded image recording system. The optical fiber, PCIE, gigabit networktransmission, DVI display technology, and remote management technology based onWEB server are researched and realized respectively. The results show that theconsecutive write speed is up to1260MB/s, the storage capacity is up to4TB. In the endof this paper, the compact military ATR recording system is researched. The3U CPCIErecording module scheme is proposed and drew. The system can obtain different recordperformance according to increase or cut the record module according to the specificdemand.