Design And Analysis Of Power Integrity In High Speed PCB

Because of the noise current which generated by Simultaneous Switching Noise(SSN),power integrity(PI) problems now have became a key factor to restrict the whole high-speed digital system's performance.Power/ground plane in device package and PCB as an integral part of the power distribution system(PDS),it provides coupling path for these noise current.So a well designed PDS is extremely important to guarantee the performance and stability of the whole system.In order to design a well PDS,accurate and fast analysis of PDS and optimization of plane noise is very important.While adding decoupling capacitor in PDS is a major and feasible method to improve PDS's performance and ensure the power integrity of system.Power distribution network(PDN) constituted the largest and most complex interconnection-layered architecture of the high-speed digital system,it accounts for about 30%～40% of interconnect space.All the devices in system are connected to PDN directly or indirectly,and there are thousands of devices in system,so the design of PDN and analysis of power integrity is the most complex part of digital system design.PDN design is the core of high-speed digital system design,it affects the power integrity,signal integrity,electromagnetic integrity and other system performance directly.This paper is focused on researching of PDN design and analysing of high speed digital system's power integrity,and then discussing power noise's suppression and PDN components'modeling and analysis which closely contact with it.Finally using Cadence Power Integrity tools Allegro PCB PI to complete a actual PDN design.