Research On FPGA-based Real-time Correction Method For Wideband Signal In TIADC System

In traditional physics experiments,a series of methods have been developed to measure the charge and time information of the detector output signal,but these parameters can only characterize limited signal characteristics.If the original waveform of the signal can be obtained,all the physics information contained in the signal can be extracted through waveform analysis.Therefore,waveform digitization is what physicists have always dreamed of,and it is also a research hotspot in the field of physics experiment electronics design.With the development of high-speed Analog-to-Digital Conversion(ADC)technique,the sampling rate of ADC is getting higher and higher,but it still is not adequate in some special applications.As a result,the development of Time-Interleaved A/D Conversion(TIADC)technique not only plays an important role in the ADC Integrated Circuits(IC)design to improve the sampling rate,but also allows us to use multiple ADC chips with a limited sampling rate to achieve a much higher equivalent sampling speed for the overall system.However,the mismatches(Gain,Time-skew and Offset)between multiple parallel sampling channels in the TIADC system is a major obstacle in improvement of system performance,and therefore the issues due to mismatch errors must be addressed in order to ensure the TIADC technique is actually practical in applications.So correction technique for these mismatch errors is an important research domain.In the traditional method using perfect reconstruction technique,the correction are found quite effective in the case of narrowband input signal.However,the outputs from detectors in physics experiments are often wideband signals,so it is necessary to develop a correction method suitable in this case.This paper mainly focuses on this,and meanwhile effort were also devoted to real-time hardware implementation of the above algorithm,which is finally integrated in a single FPGA(Field-Programmable Gate Array)device.The first chapter of this paper introduces the basic concept of waveform digitization technique,and briefly reviews two branches in hardware implementation,including Switched Capacitor Array(SCA)and high-speed ADC,and especially presents the state of art in the IC design technique of high-speed,high-precision ADCs.In the second chapter,the basic functional principle and performance parameters of ADCs are introduced,and the idea of time-interleaved technique and its technical challenges are introduced.At the same time,two kinds of correction methods for the mismatch error in the TIADC system are also reviewed.One is the background correction method based on hardware adjustment with adaptive feedback or adaptive correction based on software,and the other is digital correction method with foreground calibration process.In the third chapter,the theoretical derivation of the mismatch error correction method in the case of wideband input signal is presented,and the parallel implementation structure is introduced.Simulations were also conducted of verify the feasibility of the method based on MATLAB platform.Further more,the structure of the internal Digital Signal Processing(DSP)in FPGA devices is analyzed,which provides a reference for the hardware design and implementation.Chapter Four presents the hardware design of a 12-bit 8 Gsps TIADC system,which is mainly used to verify the validity and performance of the above algorithms.Two 12-bit 4 Gsps ADCs are employed to implement an equivalent 8 Gsps sampling rate based on the time-interleaved technique and the correction algorithms are actually designed and integrated within one single FPGA.The fifth chapter introduces the key techniques in hardware design of this TIADC system,and also the architecture of the FPGA logic in detail,especially on the parallel structure of the correction algorithm.Chapter Six gives the test results of the TIADC system.In a wide frequency range up to 1.5 GHz,the overall performance of this TIADC system is almost the same with that of one single ADC chip(according to its datasheet).The Effective Number of Bits(ENOB)is better than 8.7 Bits below 550 MHz and it is better than 8 Bits from 550 MHz to 1500 MHz.The test results indicate that the proposed algorithm can significantly suppress the effect of the mismatch errors.The last chapter summarizes the work of this paper and further possible research is also discussed.