The Research Of An ASIC For The Charge Measurement Based On TOT Technique

The planned LHAASO (Large High Altitude Air Shower Observatory) project located in Yangbajing, Tibet is a big ground-based cosmic ray instrumentation. The WCDA (Water Cherenkov Detector Array) is an important detector in the LHAASO project.The read-out electronics system needs to process the whole3600channel of PMT data, and give the charge amount and the trigger time point. The dynamic range of the charge measurement is from single P.E.(Photo-Electron) to4000P.E. A5%precision of the charge measurement is required for the4000P.E., and50%is required for the single P.E, According to the requirement of LHAASO, the front-end charge measurement ASIC chip with a4000times dynamic range was designed.The chapter1introduces the history and techniques of the cosmic ray detection. Several famous cosmic ray instrumentations around the world are introduced, especially the LHAASO project and the WCDA of it. The second chapter discusses the advantages of different charge measurement methods through several typical charge measurement chips such as the SFE16, NINO and CLC101. The time digitizer used in particle physics experiments is also discussed. It can be used to measure the time point of the trigger signal, and to measure the pulse width of the TOT output signal. The TOT technique is a method to measure the charge amount.In the chapter3, the architecture of the QTC (charge-to-time converter) aiming at the LHAASO project is designed, according to the SFE16, CLC101and other QTC chips. A simulation and analysis of the feasibility is done with this method. The chapter4introduces the main circuit blocks in this QTC chip, such as the operational amplifier, LVDS output driver, voltage discriminator, the DAC, and so on. The simulation of these blocks is also done. The parameters of several circuit elements are also discussed here.The pre-simulation and post simulation of the four channels in the QTC chip are finished. The chapter5and chapter6analyze the precision of the charge measurement, and also give a discussion about the baseline fluctuation and the rejection ability to the noise of the power supply and the reference voltage. The layout and the package of the chip are also introduced in chapter6.The chapter7introduces the PCB designed for the test of the QTC chip. A serial test will be done relying on the test board and the following time-to-digital board with an HPTDC chip. A serial initial test of the first channel is finished, and the precision of the charge measurement is obtained. The lower bound of the input amplitude which satisfies the5%precision is about6.54mV when influence of the noise and changing of the rising time is considered. Other three channels also work as expected, the performance of charge measurement is being tested. The chapter8introduced the architecture of the QTC based on the linear charge and discharge of the input charge upon a capacitor. The design of the kernel circuit blocks such as the high speed current discriminator, the digital control module is also discussed. The initial pre-simulation results are analyzed, and several problems need to be resolved are discussed.Based on the test and analysis of the first TOT method, and the simulation of the second TOT method, a summary about these two TOT methods is given in the last ninth chapter.