Investigation On STI-LDMOS Devices Based On 3-Dimensional Electric Field Modulation

Power integrated chip(PIC)is integrated power device,driver circuit,protection circuit and input/output circuit into one chip,which is widely applied in vehicle electronic,industrial control,major appliance and etc.Lateral Double-diffused MOS becomes the core of the PIC because of its high breakdown voltage,low on-resistance,high input impedance and easy integration.In order to reduce the conduction loss of the LDMOS,improve the switch efficiency of the PIC,how to reduce the on-resistance becomes the key of device design.However,the performance of LDMOS still has a distance from the‘silicon limit'.The on-resistance can be improved further.Meanwhile,the LDMOS always operates at the states of the high electric field and large current and it faces severe reliability problem that limits the application fields.In order to overcome those problems,considering the benefits of simple structure and high process compatibility for STI,this thesis focusing on STI-LDMOS establishes high accuracy electric field model,proposes new structures,explains the inner mechanism of HCI,ESD and E-SOA,aiming to guide the high performance and high reliability design.The main research results are as follows.1.Considering the structure feature of the STI-LDMOS,the two and three dimensional electric field model has been established by divided section method.Compared with the TCAD simulation results,the accuracy of the model is 88.3%and can guide the design of STI-LDMOS theoretically.2.A stair STI-LDMOS is proposed by broadening the silicon region near the drain side to reduce the parasitic resistance through the current trail.Because broadened silicon region is far away from the breakdown point,it has no influence on the breakdown voltage of the device.The MPW results show that the breakdown voltage of the stair STI-LDMOS is 33.4V and the specific on-resistance is 14.6 m??mm².Compared with the split STI-LDMOS,the specific on-resistance is decreased by 5.5%.3.A H-shape STI-LDMOS is proposed by adding a small STI into partial drift region and the STI exhibits H shape.The H-shape STI improves the breakdown voltage effectively due to the multi-direction dielectric RESURF effect,which can have more room to decrease on-resistance.The MPW results show that the breakdown voltage of the H-shape STI-LDMOS is 34V and the specific on-resistance is 14.2m??mm².Compared with the split STI-LDMOS,the specific on-resistance is decreased by 8.4%.4.It is explained that the reason of severe on-resistance degradation of stair STI-LDMOS under the I_bulkmax stress is that the stair STI corner brings in extra impact ionization peak,making the zone of interface state generation increase.The reason of slight on-resistance degradation of H-shape STI-LDMOS is that the small STI reduces the damage region of STI corner and it cannot bring in extra damage region.5.The reason of the strong ESD robustness of H-shape STI-LDMOS is that the uniform current distribution reduces the generation of Joule heat.The reason of the weak ESD robustness of split STI-LDMOS is that the crowded current in the low-resistance silicon region makes the Kirk effect strong,rising the lattice temperature.The widened silicon region reduces the current density,decreasing the generation of Joule heat.Thus the ESD robustness of the stair STI-LDMOS places the middle rank.