FPGA-Based Acceleration Technology Of Integrated Circuit’s Formal Verification

Analog and mixed signal circuits are widely used in many applications include consumer electronics, telecommunications, medical electronics. Furthermore, in deep sub-micron design, physical effects might undermine common digital abstractions of circuit behavior. Therefore, it is necessary to develop systematic methodologies to formally verify analog and mixed signal design using circuit-level models. This dissertation uses a formal method for circuit-level verification. This approach is based on translating verification problems to reachability analysis problems. It applies nonlinear ODEs to model circuit dynamics using modified nodal analysis. Forward reachable regions are computed from given initial states to explore all possible circuit behaviors. Analog properties are checked on all circuit states to ensure full correctness or find a design flaw.As circuit system verifications are required in nonlinear ordinary differential equations’ model,Coho’s formal verification algorithm is implemented in FPGA hardware to increase the computational speed.Anovel method to implement Coho on FPGA is proposed. The Sysgen tool is used to rewrite the Coho algorithm.In this way, the solution of the Coho is transformed to the design of the corresponding hardware circuit.Therefore,a suitable circuit can be designed to implement the Coho menthod. Experimental results show that,compared with the software implement mentation,the hardware implementation of Coho obtains about 10 times speedup.This study can further widen the application field of Coho,and especially extend it to the fields that are not applied before due to the computing ablility.