System and Gate-level Dynamic Electrothermal Simulation of Three Dimensional Integrated Circuits

Three dimensional integrated circuit (3D IC) is a promising technology which has potential to achieve higher device densities than technology scaling alone while improving energy efficiency. Furthermore, it can broaden the horizon of what a system-on-chip can achieve by providing the capability to integrate disparate integrated technologies on a single chip. However, the major drawback of the 3D IC is the increased power density and thermal resistances leading to higher chip temperature which is imposing several implementation challenges and restricting the widespread adaptation of this technology. In order for this technology to succeed, it is of utmost importance to model, study, and address potential problems that may arise from the complex physical dynamic interaction between electrical and thermal effects at various stages of the IC design process. In this work, techniques for dynamic electrothermal simulation of 3D ICs is explored at the system and gate-level design abstractions. A physically aware systemlevel flow is presented which allows analysis of the electrothermal tradeoffs between various design choices for 3D integration ranging from the architecture to the physical level. Based on the proposed flow, an open-source toolset, Pathfinder3D, is developed for fast electrothermal evaluation of through-silicon via-based digital architectures. The applicability of the proposed flow is shown using an example stacking of two processor cores and L2 cache in two tier 3D stack. At the gate-level, this work is primarily focused on reducing the computational cost of transient electrothermal simulation enabled by compact electrothermal macromodels of standard cells. A parallel transient simulation technique for multiphysics circuits is presented which facilitates parallel computation with multicore processors by decomposing a circuit into small subcircuits utilizing the inherent delay present within a circuit and between physical domains. A detailed simulation flow, multithreaded implementation, and examples showing superlinear speedup compared to unpartitioned single core simulation are presented.