Mechanism Of Plasma Charging Damage On Gate Oxide

Early in the introduction of plasma processing in silicon IC manufacturing, people became aware of the potential danger due to plasma damage to the devices. Much effort had been devoted to understand the damage mechanisms and to find ways to fix them. There is a lot of literature on the subject. A high electrical field apparently developed across the gate-oxide of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) during plasma processing. This high electric field leads to gate oxide breakdown or wear-out (lifetime shortening). After many years of research and development, the basic mechanisms are largely understood, although there are still mysteries.It is reported that most of the damaging plasma processes show diminished (measurable) impact when gate oxide has been scaled down to 3 nm or less in thickness. But in 0.18μm FSG process, we found that BEOL process could damage 3nm gate oxide severely. Reliabity test like GOI (gate oxide integrity) and TDDB (time dependent dielectric breakdown) degrade obviously.In this paper, the test structure and test method for plasma charging damage is studied. The direct test of gate lekage current (gate voltage is 1.1Vop) is found to be an effective and reliable way for plasma damage qualification.Based on 0.18μm cmos process, this paper made a comprehensive evaluation of all the plasma process in BEOL (including Metal etch,Poly etch,Via etch and IMD deposition). IMD (USG&FSG) deposition is found to be the main cause of plasma damage. It is found that the photonconducting effect at the end of IMD deposition make the IMD insulator leaky, the resistance of thick oxide layer is much lower in a short time, leakage current flow across IMD layer and gate oxide, generating defects in gate oxide and degrade its reliability. By increasing the thickness of IMD layer, photoconducting current at the end of the deposition is reduced (gate leakage current failure rate is changed from 60% to 20%); through adjusting the gas composition of the react chamber at the end of deposition, the photonconducting is inhibited to some extend. By the combination of these two measures, adjusting the process parameters, plasma charging damage has been significant improvement (failure rate dropped to 10%). In addition, different polarity of the charging current has different impact on MOSFET threshold voltage.