LDO Design For GPS Radio-frequency Chip

With the development of electronic technology, integrated voltage regulator is an indispensable part of a variety of electronic equipment. Linear regulator has been widely used, as it has very low noise, high power supply rejection ratio and simple structure. More and more chips are integrated with low dropout linear regulators, for it can provide a stable power supply voltage.This thesis presents the design and implementation of an on-chip low dropout linear regulator, which is integrated into a GPS radio-frequency chip. Modules in RF chips are very sensitive to the noise of power supply voltage, so it's necessary to reduce the LDO output noise, and increase the PSRR. The noise and PSRR of LDO is dominated by the bandgap reference.To reduce the intrinsic noise and increase the PSRR of the LDO, the bandgap reference with an RC low pass filter can be adopted,and an outside capacitor is available for the RC low pass filter, which can largely reduce the output noise and increase PSRR of the LDO. In order to reduce the power consumption, a switch is adopted to shutdown the LDO when the GPS radio-frequency chip is free. This LDO is designed to have a maximum output current of 50mA,as the GPS radio-frequency chip has a 15mA current consumption,and its layout area should be the smaller the better .The simulation results shows that the maximum output variation is smaller than 5mV at a full current change from 0mA to 50mA,the PSRR of this LDO is 73.7dB at the frequency of 1kHz,and more than 36.6dB in all frequency bands, the output noise is 33.5 nV /Hz @100kHz and 8.72 nV /Hz @1MHz, and the layout area is 280μm×150μm.This LDO is fabricated in TSMC 0.18μm mixed-signal process.