Design Of A Dual-mode Cochlear Implant System And Its Low Power Digital Signal Processor

Based on the research on architecture design for cochlear implant (CI) and low-power design for CI-dedicated digital signal processor (DSP), a new CI system with an implantable DSP and dual working modes is proposed. This system can choose to work in either inside-body single-machine mode or inside- & outside-body combined-machine mode when needed. As the proposed system uses only outside-body battery in combined-machine mode, the usage of implanted battery is reduced, thus it is more feasible than purely fully-implanted systems. Moreover, the limitation on the wireless data bandwidth which exists in traditional systems becomes null as only voice data with low data rate need to be transmitted via the wireless channel in the proposed system.An application-specific instruction-set processor design method based on open-source hardware (OSH-ASIP) is proposed. Detailed design flow is drawn and used in a practical DSP design. The open-source hardware design method helps to promote design efficiency and reduce cost, and the application-specific instruction-set processor design method helps to remove redundancy in general-purpose processor and thus promote the execution efficiency and reduce power dissipation of the processor. The practical design and implementation result shows that, the OSH-ASIP method combines the above two merits and builds the foundation for the success of the low-power DSP design in this dissertation.A loop cache method and a function-based memory partitioning method are proposed to reduce power dissipation of the memory. The former is very effective for application programs with aggregate short loops, and the latter is mainly applied to data memory with data functionally grouped. Actual simulation and measured results show that, proper joint application of these two methods can reduce the power dissipation of the memory in the DSP by more than 50%.Under the guide of the OSH-ASIP design method, a CI-dedicated low-power DSP is designed and implemented in 0.18μm CMOS process, with various low-power techniques including instruction-set reduction, wait mode, loop cache, memory partitioning, operand isolation and clock gating. Measured results show that, the DSP consumes very low power, which is less than only 2mW when executing the continuous-interleaved-sampling (CIS) algorithm at a clock frequency of 10MHz.