Investigation And Implementation Of Key Technologies For Wireless Sensor Network Node Chip

Wireless Sensor Network(WSN)has been widely applied in military purposes, environmental monitoring and forecast, security surveillance and so on. With the rapid development of modern silicon technology and Very Large Scale Integration (VLSI) technology, it is possible to integrate different circuits into one single chip, as a WSN node SOC solution. As the requirements of complex applications growing rapidly, the need for high performance is increasing as well as low cost, while the low power consumption is also a key issue. In this thesis, several key technologies of WSN node SOC are investigated.At architecture design level, several key technologies are described in detail. Besides using dynamic power management technology to reduce power consumption, the embedded 8-bit Micro Control Unit (MCU) is optimized by independent instruction bus and data bus, and a two-stage pipeline feature is added to achieve low-cost and high-performance. Compared with the existing standard 8051 core, the enhanced one-cycle MCU is still compatible with standard 51 instruction sets, while providing ten times efficiency. Moreover, in order to achieve more program and data storage space without increasing the volume of physical memories, a configurable distributed memory mapping method is employed.On following specific circuits design plot, some key technologies are adopted. In physical layer circuit, aim to improve the embedded LDO (low dropout regulator) system stability, we implement a dual-loop structure, and add a positive feedback loop to accelerate the circuit transient response. In order to reduce power consumption, the referenced circuit is designed to operate on the subthreshold region other than the traditionally used saturation region; Meanwhile, after analyzing the curve characteristics of crystal oscillator frequency offset and temperature, we resort to a self-calibration algorithm based on divide-frequency chain, the self-calibration circuit is implemented by a series of look up table registers that trim the input clock frequency for this SOC chip.As to MAC layer circuit, to achieve the required speed for resource-limited embedded applications, a novel CSMA/CA coprocessor is implemented, based on IEEE 802.15.4 protocol and CSMA/CA algorithm for channels'competitive access. The CSMA/CA coprocessor is designed to cooperate with the enhanced 8-bit 8051 microcontroller, using independent instruction sets to control the RF access flow by software. A Pseudo-random number generator circuit and a CRC circuit are reused through assigning different value to two registers: RNDH and RNDL. Toward the limitations of existing S-box circuit, a power attack model of AES coprocessor is established, and a novel byte substitution circuit is proposed against CPA attack, using inhomogeneous S-boxes rather than fixed S-boxes.Finally, in order to achieve high fault coverage, and with low test power at the same time, different low-power DFT techniques are adopted for different circuits. By the method of hardware and software co-verification, a FPGA verification platform to communicate with CC2420 is presented.