Font Size: a A A

Design And Testing Of High-performance Dedicated Digital Coprocessor

Posted on:2010-05-14Degree:MasterType:Thesis
Country:ChinaCandidate:B PangFull Text:PDF
GTID:2208360275982759Subject:Circuits and Systems
Abstract/Summary:PDF Full Text Request
CORDIC algorithm contain simple addition and shift operations to be completed on the trigonometric functions, exponential function and logarithmic function, such as calculation of transcendental function, and the algorithm is a rule-based algorithm, simple structure, can be easily achieved in hardware. Currently CORDIC algorithm has been successfully applied to FFT, DCT, digital signal processing and other fields.This paper will study the design of a dedicated high-performance digital co-processor; the co-processor design goal is to ultra-high-speed operation beyond the specific function. Rather than deal with all of the digital computing, so that the number of simple computing to the general-purpose CPU to deal with, so that you can use a dedicated low-cost high-speed real-time signal processing requirements, and at the same time the design of embedded coprocessor test system performance The system is capable of accurate measurement of a single co-processor computing time, burst time and many co-processor computing the average operating current. The innovation of this topic is that of co-processor low-power, high-performance design put forward the concept of dynamic digital circuits. CORDIC algorithm to hardware implementation of three modes: the order of the calculation model, the parallel cascade model of pipe line mode time-sharing the same load to the FPGA logic cells, and without increasing the hardware resources, the low-power and high - to an organic combination of performance FPGA, and the practical application of the system has broad prospects. The research of high-performance dedicated digital co-processor and its testing system is divided into the following sections:1. FPGA-based high-performance low-power digital co-processor hardware system2. CPLD based on the number of co-processor hardware system circuit configuration ISP3. MSP430F2418 processor based on the number of co-processor hardware system test platform4. CORIDC algorithm based on the number of the three co-processor core software 5. ISP circuit configuration software6. The number of co-processor software system test platformFinally, the number of different modes of co-processor performance and power consumption compared to the follow-up study has laid a good foundation.
Keywords/Search Tags:CORDIC algorithm, coprocessor, FPGA, Dynamic configuration of digital circuit
PDF Full Text Request
Related items