Research On High Performance And Low Power Design Of Embedded Memory Management Unit

With the development of complicated embedded applications, memory management has become the focus and the difficult part of HW-SW design in high-end embedded processors. Virtual memory technique is an effective memory management method, which is transparent to software based on operating system. This can simplify the memory management mode and enhance the portability of application software. Meanwhile, memory management unit (MMU), the major concern of power consumption and area cost of embedded processors, is implemented in hardware to realize virtual memory technique. In this thesis we propose some key techniques of embedded TLB for high performance and low power implementation of embedded MMU. The original contributions of this thesis are as follows:1. A TLB design method based on cache resource reusing. This thesis analyzed the similarity between TLB and Cache entry in storage structure and accessing behavior, and then proposed a new TLB design method based on reusing cache hardware resource for lower power consumption and smaller area cost in embedded processor. This method set up cache address mapping table, which recorded the location of TLB entry in Cache, to decrease TLB accesses with less dynamic power consumption.2. An innovation of multi-process TLB entry sharing one cacheline window. This method partitions cacheline into different process windows to prevent frequency replacement of TLB entry during process switch. Dynamical TLB entry extension based on cache architecture enlarged the mapping range of physical address for higher TLB hit rate and provided a solution to TLB entry restriction in traditional TLB design. Moreover, an entry locking method of TLB was also proposed to balance the resource hazard in maximum degree between TLB entry and instruction/data.3. Two-level low-power TLB implementation with multiple TLB page sizes supported. This method utilized two-level TLB architecture to solve cache access hazard between TLB and instruction/data, with great dynamic power saved when accessing in-cache TLB. Two page sizes could be dynamically supported by extending the first level TLB entry for higher TLB hit rate. Compared with traditional TLB design, experiments show that the proposed method reduces the power consumption and area cost of embedded processor by 28.11% and 21.58% respectively, with comparable performance achieved.Techniques proposed in this thesis facilitate the implementation of embedded processor, and have positive effects on performance, power and area.