AES Coprocessor Implementation For Wireless Sensor Network

Wireless Sensor Network ( WSN ) has wide application in military affairs, environmental monitoring and forecast, security detecting and so on. The Advanced Encryption Standard (AES) is used as an authentication and cryptographic algorithms for WSN. How to design a low-cost high-security AES coprocessor is one of the key issues of WSN.Based on the research and analysis of the security system of WSN, we present a low-cost high-security design of AES coprocessor. In detail, different standard-cell implementations of the substitution box (S-box) and a compact architecture with four S-boxes are presented, and inhomogeneous S-boxes instead of fixed S-boxes are randomly selected to randomize power consumption, based on the discussion of AES hardware implementation and power analysis theory.In this dissertation, the AES coprocessor circuit is described with Verilog HDL. The function simulation and synthesis are performed by using EDA tools. Furthermore, attack simulations are illustrated by Correlation Power Analysis (CPA). The result demonstrates that this scheme has very low hardware cost, moreover, it enhance the AES secure characteristics against power analysis effectually.