Design And Implementation Of Block Cipher Coprocessor For Anti-power Attack

In recent years,the cipher coprocessor about information security faced with more and more serious security challenges.The Side channel attack with the release of all kinds of information in the process of password chip operation attacked.Due to low cost,easy operation,high efficiency and so on,the Side channel attack become one of the biggest threats to the physical security chip.The power consumption is one of the most widely spread the most practical means of attack.This attack method has universal applicability,used to attack various encryption algorithm.At present,the widely used linear block cipher DES and AES / 3 DES also threatened by power consumption.In this paper,RTL-level block cipher coprocessor is designed and implemented using pipelining and module reuse techniques.Each round operation is carried out module encapsulation multiplexing,round operation between the pipeline,the S core are used combinational logic,rather than lookup table.In the DES cipher module,the random number difference or masking technique is used.The AES cipher module uses the random number or masking technique and random pseudo-operation to realize the function of anti-power attack.And the mode of the block cipher coprocessor includes ECB and CBC.The coprocessor is based on the AHB bus,easy to mount the SOC chip of the ARM core.The simulation results show that the coprocessor function is normal,operation speed is excellent.Increased resistance to attack power consumption structure,the coprocessor can resist second-order DPA attack power consumption,and the part of the area overhead increment is less than 10%,the performance of the operation is not affected.To verify the feasibility of the design technology of the resistance to attack power consumption,effectiveness and simplicity.The processor can be used in all kinds of the ARM architecture SOC platform,including smart cards,Internet,etc.