Research On Application Specific MPSoC Design Flow And Platform

Fast development of embedded application drives MPSoC design more complex.Therefore how to design MPSoC efficiently and reliably is now becoming a main challenge to IC design.This dissertation focuses on the research on application specific MPSoC design flow,methodology and platform to address current system-level design problems.In this dissertation,a new MPSoC design flow and platform is presented for software and hardware concurrent design from application algorithm to physical implementation.The experiments of audio and video codec are also given to verify proposed design flow and platform.The research work covers the following four aspects:1) CKSoC platform and its coarse-granularity SoC design flow.CKSoC platform is built based on CKCore processor and AMBA bus for SoC low-level hardware integration and verification.CKSoC platform makes use of SPIRIT-based IP library to achieve great compatibility with other IP and SoC EDA tools.The design flow based on CKSoC platform can support manual coarse-granularity partition on given application and provide platform configuration parameters to generate target hardware platform rapidly.The complete hardware and software co-simulation on FPGA prototype can validate the system function and performance exactly.Furthermore,the SoC design for two applications,H.264 intra-frame encoder and OGG decoder,is presented to show the feasibility and effect of CKSoC platform and its design flow for hardware/software partition and heterogeneous dual-processor SoC design. 2) Simulink-based MPSoC system level design flow.Simulink-based MPSoC design flow is a higher system-level design flow based on CKSoC platform to meet the requirement for fine-granularity, high-complex and high-performance MPSoC design.The proposed design flow enables systematic and automated MPSoC design from a high-level algorithm specification to low-level implementation using the Simulink environment and SystemC language.During gradual refinement,the functionality and performance of software stack and hardware architecture can be validated step by step.For seamless hardware and software refinement from application algorithm to RTL implementation,four different-level combined algorithm/ architecture models (CAAM) are used to specify abstract hardware and software architecture: Simulink CAAM for high-level algorithm and architecture specification,virtual architecture CAAM for early development and validation of the multithreaded application software,transaction-accurate architecture CAAM for fast verification of hardware architecture and OS library,and virtual prototype CAAM for accurate system verification and performance estimation.3) Simulink-based MPSoC design platform and its multiprocessor prototype.The software and hardware platform for Simulink-based MPSoC design flow supports some different processors,such as ARM,XTENSA and CKCore,and some communication architecture,such as GFIFO,HWFIFO and DMS,which improves the configurability and flexibility of proposed design flow and also guarantees the range of MPSoC architecture design space.Moreover,this platform also involves some special technique for optimizing memory and communication usage:improve the communication efficiency and reduce communication load by use of refining inter-processor communication architecture and optimizing multithread communication channel;improve the memory efficiency and reduce memory size and power by use of optimizing the multithread scheduling and hardware memory architecture;obtain the proper performance estimation for architecture exploration by use of systematic and effective performance analysis.Based on this platform,a new multiprocessor prototype is presented to combine computation and communication into one multi-layer software and hardware prototype.This multiprocessor prototype can also work as a reusable processor architecture prototype with configurable and flexible software/hardware architecture and interface.According to the application requirement and software/hardware co-simulation result,we can configure and adjust the multiprocessor software and hardware architecture to obtain best system performance.4) Case study of video decoder application to verify the proposed system-level design flow and platform.The experiment of Motion-JPEG shows the feasibility and effectiveness of multi-level modeling and its gradual refinement in Simulink-based MPSoC design flow.Moreover,the design flow and environment is further proven to be adaptive,flexible and efficient to different processor types and inter-communication mechanisms.In the experiment of H.264 decoder,the MPSoC archicture will be refined gradually from coarse-granularity partition to fine-granularity partition.Furthermore,it also proves the effectiveness of those techniques for memory and communication optimization used in multithread code generation.Finally the multiprocessor prototype is implemented by use of both FPGA chip and SMIC process,to verify the physical feasibility of proposed design flow and platform.