An Embedded System With The Architecture Of Chip Multiprocessor And Component-Based Software

Along with the development of the semiconductor manufacturing and thein-depth research on the computer architecture, the multi-core (also called CMP,Chip Multiprocessor) technology will be widely used into the design of theembedded system chips, which generally makes Thread-Level Parallelism (TLP)spread in the fields of the embedded system software. This takes a revolutionfrom hardware, operating system, compiler to software development without thedefinite solutions yet. So this is the focus of the recent research on the embeddedsystem fields.Generally speaking, the heterogeneous CMP architecture is usual for theembedded system. The thread support, thread scheduling, interrupt support anddevice management are also changed in the Embedded Operating System (EOS).For the software development, thread library, parallel programming language orcomponent-based software is used to write the parallel programs.With the extension of the embedded system, intensive computing will alsobe widely used in the embedded devices and the flexible string matching is one ofthe most representative applications. How to design a customized chip to improvethe performance of the embedded system is the starting point of this research.In the embedded system, to deal with the intensive computing, especiallywith the requirement of the string matching, hardware/software co-design isexplored to improve the heterogeneous CMP embedded system. For the hardware,the research focuses on the intensive computing optimization; for the software,the research focuses on the component-based upgrade for the CMP architecture.In this thesis, the contributions include:First, the heterogeneous CMP is designed with the on-chip high-speed bus,which has a Synergistic Processor Element (SPE) with SIMD instructions to dealwith the computation-intensive applications, especially for the hardware-aidedstring matching. The cross-core communication mechanism is designed to keepthe stable and efficient communications.Second, the SPE is driven by EOS and the Board Support Package (BSP) isre-designed as Cross Platform BSP Framework (CPBF) to encapsulate the hardware. The programming model of the SPE is also referred to guild theparallel software development.Third, the Thread-Level Component (TLC) model is established toencapsulate the thread, the TLC usage and the parallel assembly strategies arediscussed. As the embedded component, the TLC model also includes therestrictions of the none-functional properties and a component reuse frameworkis designed to guild the efficient split, maintenance, development and reuse of thecomponent.These designs are critically examined with several experiments on thesimulator and the hardware development board. The algorithm of the hardwareimplementation is proved in the reduced cycle-based simulator. With the SoCintegration, the whole software/hardware solutions execute on the Xilinx ML 403FPGA development board, an application for the binary data matching is carriedout to show the transportation of CPBF and the accelerations with SPE. The TLCmodel can be examined in these applications. Finally, the dynamic configurationsof the embedded software are also examined with the spilt and assembly of thesimple component-based protocols as an example.In this thesis, the research focuses on the design of the parallel programmingand the dynamic scheduling of the CMP architecture based on component-basedsoftware to encapsulate the thread; explores the new method of hardware/software co-design to deal with the computation-intensive applications. Theseimprove the hardware and software research of the embedded system based onthe CMP architecture and the component-based software.