Research On Key Techniques Of Network-On-Chip Design For Multiprocessor System-On-Chip

With the development of IC fabrication technology and the increase of application requirements, SoC systems in the future will become even more complex and integrate hundreds of processing cores into a single silicon chip. For such Multi-Processor SoCs (MPSoCs) with high integration and large complexity, one key issue is the on-chip communication among various cores. Thus, design of on-chip communication architectures that can provide high performance, low power and good scalability for future MPSoCs has become a recent research thrust.Traditional on-chip communication structure, such as buses, cannot satisfy the communication requirements of future MPSoC due to various limiting factors as weak scalability, low energy efficiency and small bandwidth. The layered design methodology based Network-on-Chip (NoC) technique provides a new solution for communication problems of MPSoCs. With the layered communication abstraction models for NoC, this dissertation focuses on the design and optimization in the physical-link layer, network layer and system layer of the on-chip communication fabrics in MPSoCs. The main works of this dissertation are as follows:1) In the NoC physical-link level, we first present a novel temporal encoding technique, called dynamic-insert-shield-pattern (DISP) coding, for global inter- connects that enables higher performance while reducing energy dissipation. This technique is based on an efficient temporal encoding circuit that dynamically builds appropriate shield signals depending on the current and previous states of input signals to separate temporally adjacent data, achieving the objective of eliminating opposite transitions on adjacent wires as well as reducing the number of coupling transitions. Then, by combining this temporal encoding technique with the spatial bus-invert (BI) coding, we also proposed a spatial and temporal encoding technique, called BIDISP coding, to further improve energy reduction. This technique has a highlight that the BI spatial encoder is based on a novel majority voter circuit with desirable merits such as high-speed, low-power operation and near-zero static power, thereby, resulting in significantly reduced energy and delay overhead of spatial encoder. Experimental results show that the both encoding techniques can reduce interconnect delay and energy dissipation effectively.2) Aiming at optimizing interconnects in the physical-link layer, we present a repeater insertion optimization method to determine the proper repeater size and insertion interval along the interconnects which minimizes the total bus energy dissipation while satisfying target delay and slew-rate constraints. In the process of optimization, we adopt an efficient GA-SQP mixed algorithm which shows good capability in guaranteeing precision of the optimal solution and accelerating converging speed. This method can be used to rapidly obtain optimal energy vs. delay trade-offs under slew-rate constraint for DISP and BIDISP encoding techniques. Experimental results show that compared to SPICE simulation, this optimization approach achieves the accuracy of more than 90% and approximate 45 times calculation speed improvement.3) In the network layer of NoC, we propose a low latency and low power Virtual Channel (VC) based wormhole-switched router architecture for basic Best-Effort (BE) services. This router supports both the deterministic and adaptive routing algorithms, simplifying the out-of-order issue induced by the adaptive routing. Also, it allows all the VCs to participate in output scheduling in parallel which enhances the probability of successful scheduling significantly. Integration of VC allocation and switch allocation in the same pipeline stage increases veracity of the adaptive routing decision and the mechanism allowing multiple packets sharing a single VC increases buffer resources utilization while lowering the network latency. Besides, the proposed VC allocation scheme not only avoids routing deadlocks, but also reduces area overhead in that the internal crossbar structure is simplified from one traditional 5X5 switch to two weakly-coupled 4X2 switches. The objectives of our router architecture to effectively reduce average network latency, power dissipation and area overheads are achieved from experimental results.4) Also in the NoC network layer, we propose a virtual circuit based BE/GS router architecture providing hard performance guaranteed for Quality of Service (QoS). This router structure employs one adaptive routing based setting-up policy with back-way mechanism which improves success rate of the distributed setting-up process of GS virtual connections. In the GS data transfer stage, we adopt one connection-oriented QoS scheduling algorithm and prove its correctness theoretically. By dynamically adjusting priorities of GS connections in each router in distribution, this algorithm effectively resolves transfer conflicts between different GS connections sharing the same physical link, and hence guarantees such QoS requirements as latency, bandwidth, jitter, etc, and supports various bandwidth applications, realizing multiple differentiated bandwidth-guaranteed services. Besides, through dynamically allocating priorities to BE channels and monitoring GS data flow, the quality of BE services is improved and the shortcoming of virtual circuit—low resource utilization is overcome.5) In the system level, the research object becomes the entire MPSoC system comprising application software and hardware platform (including processing cores and the communication network architecture), rather than the unitary on-chip communication architecture. Based on the"firm"NoC platform, we propose an energy-aware software/hardware co-synthesis algorithm for a heterogeneous NoC system, which implements software (task allocation, task scheduling and routing path allocation) and hardware (PE mapping) co-design under the constraint of performance requirement with the aim to minimize the sum of the total execution energy and the total communication energy. The synthesis result generated by this algorithm is validated with a SystemC written, cycle-accurate NoC simulator. A Dynamically Voltage and Frequency Scaling (DVFS) technique is applied to the synthesis result to further reduce the total system energy. Experimental results show that significant energy savings can be achieved by using this co-synthesis algorithm while applications'real-time requirements are meted.