Research On TSV Array Fault Test Method Based On Time To Digital Converter

The continuous reduction in the feature size of interconnection has made performance problems caused by interconnections increasingly prominent,and has made interconnection issues become a bottleneck in the development of integrated circuits.3D integration technology can shorten the interconnection length significantly,reduce interconnection delay,improve the integration of the system,and provide a feasible technical solution for solving interconnection problems and the continuation of Moore's Law.As a new interconnection technology in 3D Integration Circuit(3D IC),Through-Silicon Via(TSV)realizes the signal transmission between the layers,which has attracted more and more attention.In 3D integration,the number of TSV is large,and the distribution is dense.The crosswalk coupling between TSVs will affect signal transmission performance.Moreover,the manufacturing process of TSV is complicated and immature,which can cause various defects in TSV easily and will further affect the reliability of the 3D IC.Therefore,it is necessary to analyze and test TSV to improve circuit performance and yield of TSV.The paper mainly analyses the crosstalk coupling of the TSV array and proposes a builtin-self-test(BIST)method to detect the faults in the centre copper conduction and insulation layer of the TSV.The main research work includes:1.Based on the knowledge of 3D IC of TSV,the paper establishes a physical model of TSV array and calculate the total coupling capacitance in the TSV array through parameter extraction software to reflect the size of crosstalk coupling in the array.The influence of TSV quantity changes and array edge effects on crosstalk coupling are discussed.Besides,the paper proposed four different TSV array layout structures,and analyze their near-end crosstalk with S parameters to obtain two TSV array models that are beneficial to expansion.Meanwhile,the structural parameters of the TSV array are analyzed,and the influence of the area of the TSV array is considered,which illustrates the selection rule of the TSV array size.2.The study analyses the generating mechanism of TSV faults and establishes the equivalent circuit model of TSV with and without fault according to its electrical characteristics.By changing the size of the fault equivalent resistance,the variation law of signal transmission delay and fault size is obtained.Based on Time to Digital Converter(TDC),a new TSV test method is proposed by using TSV as a load.The test circuit structure is designed and simulated in HSPICE based on the 22 nm PTM CMOS process.3.According to the proposed test method,we adjust the transistor parameters in the circuit structure,respectively detect the open circuit fault and the short circuit fault,the output digital code corresponding to the fault can be obtained.The code reflects the severity of the fault and helps to evaluate the validity of the test results.Using the principle of time amplifier,the proposed test method is improved,and the detection range and test resolution of the method can be obtained.