Research And Verification Of SRAM Stochastic Fault Injection Technology

With the continuous progress of chip manufacturing processes,new manufacturing processes have made Static Random Access Memory more complicated fault models in the manufacturing process.Presently,chip testing schemes have been getting increasingly sophisticated and a growing amount of attention has been paid to fault injection utilized to verify the coverage of testing algorithms.Despite the emergence of multiple modified built-in self-test algorithms for SRAMs,there has not been an effective method to verify the fault coverage of these algorithms.Existing methods mostly based on single-address fault injection at the register transfer level(RTL)to simulate simple fault models in order to validate the effectiveness of memory test algorithms.These methods are unable to verify the statistical fault coverage,nor can they fulfill the injection of complex fault models.Thus,designing a random fault injection technology that can effectively verify the fault coverage of test algorithms is a highly needed technological breakthrough in the current SRAM testing field.This thesis focuses on the technological problem of fault coverage validation by taking into account of the area,time and cost needed in fault injection,and proposes a random memory-fault injection technique that occupies neither extra areas nor increases the simulation duration.The thesis mainly addresses from the following aspects:(1)the structural characteristics of SRAMs and the development status of fault injection.The characteristics of existing fault injection techniques were compared.Based on the mechanism and manifestation of faults pertaining to the SRAM fault models,a specialized random fault injection technology was designed.(2)The feasibility of the proposed random fault injection technique was validated.(3)A statistical calculation was performed to verify fault coverage of the test algorithm.(4)The statistical data pertaining to coverage verification pointed to an inability of the algorithm fully cover all fault types.Thus,a modified algorithm,namely,the March?RAW1 was used to run a re-test,which satisfied the purpose of verifying the effectiveness of the improvement to the test algorithm.This thesis mainly examines the mechanism of memory fault and the memory-fault injection technique that was used to statistically verify the coverage of the test algorithm.The experiment object was a 6T SRAM based on the TSMC40 nm process.On this basis,random memory-fault injection was realized and the HSIM simulation was performed to verify the effectiveness of the fault injection.The HSIM+VCS mixed simulation was utilized to perform a MBIST test over memories that had undergone massive random fault injections,followed by a statistical analysis of all simulated waveforms.The results show that the March C+ algorithm achieved an 87.8% fault coverage in the test of resistive-open fault.The modified March?RAW1 algorithm based on the mixed simulation platform subsequently substituted this test algorithm.The analysis of the oscillogram of the simulation shows that the modified March?RAW1 algorithm can test dynamic read destructive fault that could not be covered by the March C+ algorithm,validating the effectiveness of the current modifications made in the industry to memory test algorithms.