Passive Uhf Rfid Tag Chip Rf Front-end Research And Design

Radio Frequency Identification technology (RFID) is a recently rising technology which is applied to the short distance non-contact information transmission field. It is also a new non-contact technology innovation after the barcode technology was taken into use 30 years ago. The development and achievement in Internet of Things (IOT) promotes the RFID technology to develop more rapidly in recent years. Passive UHF RFID Tags are more and more taken into applications because they are flexible, low cost and less difficult for maintenance. While operation, a passive UHF tag transfers the radio frequency power into power supply for the chip instead of using a battery, which brings itself smallest size, lower cost and convenience for transplantation. At the same time, the introduce of sensor block, security algorithm and biological engineering have enlarge the field of the application of passive tags.In this paper, the theoretical background and signal transmission path of the RFID technology is studied, which provide the explanation of the communication environment of a passive UHF RFID tag. Based on the operation environment of a passive tag, the system factors and the global parameters which are proposed for the chip optimization are also discussed, including the cost, physical size, impedance match from antenna port, power conversion efficiency, product test and package factors and protocol requirements.According to the design recommendations from system analysis, the three major techniques during the design of RF frontend are deep analyzed, including the theoretical analysis and design of the high-efficiency rectifier, the stable communication across full power scale and the optimization of the RF parameters. The theoretical modeling of a differential rectifier based on the active Vth canceling technique and a design flow of a rectifier in passive tags are first proposed in this paper.At last, a passive UHF RFID tag with a differential high-efficiency low power RF frontend is implemented in SMIC 0.18μm EEPROM CMOS technology. The measured power conversion efficiency (PCE) of the RF frontend reaches 43% at-17dBm input power level, and the measured read sensitivity of the tag chip reaches-14.5dBm. In addition, an implementation of the RF frontend in a passive UHF tag in SMIC 0.13μm RRAM CMOS technology is proposed to verify its compatibility with the security baseband and new type of RRAM memory.