CAMPER:Research And Implement On The Design Techniques Of High-Efficient Processor Core Architecture

As the quick development of computer software and hardware, high performance computing has been getting really fast advancement, which in turn requires more and more powerful microprocessors. Many challenges of hardware, architecture, programming model, algorithms, application and tools about performance, power and reliability need to be revoled when implementing future high performance computers. The performance, power and reliability of processors highly depend on the core microarchitecture. The core microarchitecture has a huge influence on programming model, algorithms and applications.This paper proposes a novel high efficiency core microarchitecture, CAMPER(Core Architecture with Multi-thread, Power-efficiency and Reliability), to resolve the performance, power and reliability challenges faced by future high performance computers. CAMPER is based on a reduced EPIC(Explicit Parallel Instruction Computation) architecture. At the same time, CAMPER features multi-thread and vector computation technique. A prototype chip, TENT, is implemented which includes CAMPER core microarchitecture with advanced low-power and high reliability technologies.This paper has the following main contributions:1) A reduced EPIC microarchitecture as a basic CAMPER core is proposed with an innovational mechanism which is in-order issue, in-order execute, in-order commit, out-of-order completion, lock-step execution model(I3OLSM). The proposed execution model can exploit effectively memory access parallelism. The complexity of the chip is further reduced with negelectable performance loss because of low-overhead instruction dispatching, asymmetric execution unit, and virtual multi-port data caches.2) Group interleaved multi-thread and vector extension of CAMPER is proposed. CAMPER utilizes vector extention to improve peak performance, and utilizes multi-thread execution to improve efficiency. Several techniques are proposed:(1) A novel instruction set and register file extension scheme, combined with masked vector execution model to reduce overhead;(2) A group interleaved thread scheduling algorithm that splits threads into groups. To improve performance, threads within a group are scheduled in a round-robin manner, and threads across groups are scheduled simultaneously.(3) A high efficient vector data memory structure that supports mixed scalar and vector access. Experimental results have proven the effectiveness of these proposed techniques.3) Energy proportional microprocessor design philosophy that reduces processor power with architecture design, logic design and physical design techniques simultaneously. A novel software and hardware codesign processor standby and sleep techniques are proposed to reduce dynamic and static power by effectively exploiting the power reduction potentials of idle components with the support of instruction extension and power management unit. An instruction queue based loop dynamic detection and execution mechanism is proposed to detect program loop codes dynamically and bypass fetch unit when a loop is detected, which can reduce power. The proposed techniques are implemented through physical design. The power of the processor is also reduced through power reclaim in physical design. Test results show that the proposed multi-level, multi-stage power optimization techniques make a good proportional scale between power and performance, and meet the goal of on-demand power consumption.4) A low-overhead soft error tolerant cache array scheme with way interleaving is proposed. In this scheme, cache data is stored in a scatter manner through way interleaving. Data scatter ensures multi-bit errors caused by single event upset occurrance in different cache lines, which makes error detection or correction possible in a time-multiplexed manner. In this way, multi-bit storage error in deep sub-micron design can be effectively resolved to improve the reliability of on chip storages.A prototype chip, TENT, is designed and implemented which includes CAMPER core. At a 1.5GHz frequency, TENT achieves a SPEC CPU INT2000 rate score of 143 and a SPEC CPU FP2000 rate score of 122 at a power of 30 Watts. These results show CAMPER is a high efficient core microarchitecture.