On Microprocessor Architecture-level Test Program Automatic Generation

Functional verification is widely acknowledged as the bottleneck of microprocessor design. Architecture-level verification can disclose failures in design flow early, which greatly reduces loss. Simulation is still the main vehicle for architecture-level functional verification. But the generation of test program for simulation by hands is very low efficient, and its failure probability is high. Therefore, the automatic generation of test program plays a major role in the verification of modern microprocessor.Existing test program generators don't verify the whole design. Their methods for making architecture model are complex. What's more, most of them can be intrinsically ranked random test program generator, which results in low verification efficiency.Based on our own framework for microprocessor architecture-level test program generation, the thesis focuses on the research of constraints satisfaction problem of test program generation and develops a novel specification driven and constraints solving based automatic test program generator. The primary work and contributions of the thesis include following three parts:Firstly, we have designed the core component of our automatic test program generator - the constraints compiler, and worked out the strategy for making constraints model. Because the compiler is independent of verified design, it can work for all kinds of microprocessors with different architecture by configuring the architecture information. Implemented by a member of our group, the constraints compiler works well.Secondly, we have advanced a new verification-oriented architecture description language -VADL, and implemented its compiler. VADL is very natural and has a good readability. It eases the capture of information for verification. In VADL, we follow a structure and behavior mixed-level approach to facilitate specification of the architecture of microprocessor, which can capture sufficient information for test program generation.Thirdly, we design the architecture feature configuration file (ACF), and we have been able to generate it automatically. ACF provides architecture information to configure the constraints compiler.Last, we design the instruction template library (ITL), which also can be generated automatically. Because ITL can help to separate the generic verification knowledge of microprocessor from that of specific architecture, our system can generate test program for many kinds of architecture.The prototype system - MA~2TG can not only generate test program randomly, but also generate specific test program. It has been successfully applied to the verification of DLX processor and LEON2 processor, and the experiment results have proved the validity of our method.