Investigation On The Blocking Layer Of The Charge Trapping Memory Device

Currently, flash are the dominant memory devices in the non-volatile semiconductor memory market. As the flash involves in the20nm nodes, the flash technology based on the conventional floating gate faces the big challenge. There are issues such as the floating gate coupling, charge leakage, the disturbing between the adjacent cells and so on. Thus, the discrete charge trapping memory is proposed to replace the floating gate memory. The charge trapping memory is composed of the tunneling layer, the charge trapping layer and the blocking layer. In order to meet the requirements of low operation voltage and high reliability, the optimization of the blocking layer is investigated in terms of materials, structure and post processing. Also, illumination is introduced in the speed measurement that minority carriers take part in the capacitor structure.This paper first introduces how to optimize the blocking layer in terms of materials. Since the conventional SiO2material as the blocking layer cannot meet the scaling down requirement, the high k material is introduced. Firstly, why to introduce the high k materials in the blocking layer is introduced. The reason is that the use of high k material in the blocking layer leads to more electric field is applied to the tunneling layer, which results in faster program/erase speed. Meanwhile, the high k blocking layer along with the high work function metal electrode can effectively suppress the erase saturation. Then blocking layers with various high k materials are introduced. Second, how to optimize the blocking layer in terms of structure is introduced. One method is to use the stacked high k blocking layer, which could combines advantages of different high k materials. Another is to insert SiO2between the charge trapping layer and the blocking layer. Since the band gap of SiO2is large, the retention of the memory device can be greatly improved without degrading the speed. Third, how to optimize the Al2O3material in term of post processing technology is introduced. Our experimental results show that the high temperature post deposition annealing can reduce the trap density in Al2O3material, which can greatly improve the performance of the MANOS device. Meanwhile, it is also found that the annealing atmosphere has an obvious effect on the MANOS device. Finally, the illumination is introduced in the speed measurement under the condition that minority carriers take part in the program or erase. Based on a relaxation time model, the time constant in the dark and illumination is extracted. Illumination can reduce the time constant. And illumination increases the program or ease speed in the capacitor structure. It is found that the speed in the capacitor under illumination is comparable with that measured in the transistor structure.