Charge-trapping MONOS Memory With High-k Stacked Gate Dielectrics

As next-generation application of the traditional floating-gate flash memory, charge-trapping memory presently faces some severe technique challenges as the technology nodecontinuously scales down, i.e. at low operating voltages, large memory window, fastprogram/erase (P/E) speed, good endurance and10-year data retention must be attained.For metal-oxide-nitride-oxide-silicon (MONOS) memory, the conventional SiO2and Si3N4are substituted by the high-k dielectrics, and hence optimization of the material, structureand fabricating processes of its blocking layer (BL), charge storage layer (CSL) andtunneling layer (TL) will be the main approach of improving performances ofcharge-trapping memory. These are just research work performed in this dissertation.Experimentally, some high-k dielectric materials as CSL are investigated and compared, thenovel dual-CSL and dual-TL structures of high-k/low-k are designed and prepared, andoptimization of the fabrication processes has been carried out to achieve a good trade-offamong the memory window, P/E speed, endurance property and retention characteristics.Theoretically, the electron-retention model of MONOS memory under the programmingstate has been established.Some investigations have been done on the high-k dielectric materials and fabricatingprocesses of the CSL:①The La-based binary-mixing oxides as the CSL of MONOSmemory are prepared by doping Hf, or Ti, or Y into La oxide and their effects on theperformances of the devices are investigated and compared in detail. It is experimentallyfound that high density of traps with deeper levels and thus high trapping efficiency, strongHf-N and La-N bonds and stable HfLaON/SiO2interface and thus reasonable data retentioncan be achieved by incorporation of N into HfLaO to form HfLaON. Compared to deviceswith LaTiO CSL, the devices with LaYO CSL exhibits larger memory window, higherprogram speed, better retention and endurance properties, suggesting that the Y-doped Laoxide could provide a large amount of bulk traps and thus high charge-trapping efficiency,and effectively suppress formation of the interfacial silicate layer near the CSL/SiO2interface during post-deposition anneal, reducing generation of shallow-level traps or defects;②Using GdO as CSL, the effects of different sputtering ambient (N2or O2) andanneal processing on quality of GdO thin film and performances of the memory areinvestigated. Experimental results indicate that the memory window is greatly increaseddue to generation of a large quantity of electron traps induced by incorporation of N intothe GdO dielectric, and furthermore, a good trade-off among the memory window, P/Espeed, endurance, and retention characteristics can be achieved by NH3annealing at5500Cfor2min, which can effectively suppress creation of shallow-level traps near the CSL/SiO2interface, and thus give suitable spatial distribution of traps with deeper energy level in thebulk of the CSL.Regarding novel stacked gate structure:①A stacked gate structure of Au/HfAlO/AlN/(HfON/SiO2)/Si is proposed and prepared by in-situ sputtering method, where the ultrathindual-TL of HfON/SiO2is used to increase speed and efficiency of charge injection, the AlNCSL with deep-level traps is employed to provide large memory window, good chargecapturing capability and stability of charge trapping, Au electrode with high work functionand HfAlO BL with suitable k value and barrier height can effectively reduce electroninjection from the control gate into CSL during erasing and leakage of those charges in CSLduring retention, thus shortening erase time and enhancing data retention.②Based onbandgap engineering, a dual CSL composed of TiON/HfON is proposed and prepared, anda tapered bandgap structure with bandgap increasing from the TL to the BL is formed dueto the inter-diffusion between Ti and Hf near the TiON/HfON interface which leads to anintermixing layer of HfxTiyON with varying Hf/Ti ratio in the dual CSL during post-deposition annealing. A large quantity of electron traps exists in the dual CSL due to themixing of HfON and TiON. The tapered bandgap structure can give a multi-level trapdistribution, which is beneficial for enhancing charge capturing capability of traps andcharge injection efficiency, thus obtaining large memory window and high P/E speed. Inaddition, a large barrier height between the TiON and TL can effectively block escaping ofthose trapping charges, enhancing data retention.Theoretically, an analytical model of electron retention under the programming state isestablished by taking trap-to-band (TB) tunneling as leakage mechanism of the trappedelectrons, assuming a triangle-like energy-level distribution of traps and considering the trap spatial distribution as the uniform or local profiles respectively. The correctness andaccuracy of the model are confirmed by good agreement of the simulated results withexperimental data.