| With the development of the semiconductor technology, the size of the memory cells is getting smaller, while the integration density of VLSIC (Very Large Scaled Integrate Circuit) is getting higher and higher. As a member of the semiconductor memories, the nonvolatile memory technology also moves toward higher integration density, higher program/erase speed, and lower power consumption. However, the traditional flash memory is facing serious challenges nowadays, due to continuous increasing of the integration density. First of all, the thickness of the tunneling layer must decrease with the scaling down, while the decrease of thickness will lead to huge local increase of the tunnel currents (namely, stress induced leakage currents), and increasing number of the anomalous failure bits. Secondly, the cell-to-cell interference may prevent the increase of the integration density. Finally, the biggest challenge is few electrons can be used for information storage. Less than100electrons will be stored in the cell when the size of memory cell is less than22nm. In this case, losing dozens of the electrons could result in a retention failure for the devices. So, it is critically important to find new memory devices for the further applications.As a newly-reported nonvolatile memory device, charge trapping memory (CTM) devices have a good developing prospect. Because of the "discrete-trap" storage mechanism in CTM device, the device has better endurance performance than conventional floating-gate device. In addition, the thickness of the tunneling layer could be thinner than that in floating-gate device. In CTM devices, the study on the charge storage and loss mechanism, and the improvement of the charge trapping capability are critically important for the further development. In this work, we prepared a series of CTM devices with different sizes of Au NCs, and studied the relationship between the size of Au NCs and the charge trapping capability of the device. The mechanism of the lateral charge loss in Au NC CTM devices was also investigated. Then, we provided an effective method to create trap sites by thermal treatment and intercalating Al2O3layers in HfO2charge trapping layer. Finally, the high-k composite oxide thin film was chosen as the charge trapping layer to further improve the charge trapping capability of the memory device. The main results are summarized as follows:1. A series of CTM devices with different sizes of Au NCs were prepared, and the relationship between the size of Au NCs and the charge trapping capability of the devices was studied. The results show that the charge trapping capability depends on the joint effect of both the size of Au NCs and the inter-NC distance. The increase of the NC sizes can enhance the charge trapping capability of the devices, and the decrease of the inter-NC distance will aggravate the loss of the charges. The device with large size of Au NCs and suitable inter-NC distance usually has a good charge trapping capability. A model with variable range hopping (VRH) and vertical charge loss mechanisms was developed to explain the decrease of the charge trapping capability in the devices when the size of Au NCs was large than4nm. The lateral hopping probability of the charges increases when the inter-NC distance gets smaller. When all the Au NCs are inter-connected, the discrete NCs-based CTM device turns into a continuous floating-gate-like memory device. Therefore, if a single leakage path (intrinsic or stress induced leakage current related) appeares in the tunneling layer, all the trapped charges will lose. In this case, only a narrow memory window is observed in the C-V curve.2. The charge trapping memory (CTM) devices based on different HfO2/Al2O3nanolaminated charge trapping layers were prepared and investigated. High charge density was obtained in the inter-diffusion layer in which additional trap sites can be created by thermal-treatment induced inter-diffusion, and a lot of charges can be trapped in this inter-diffusion layer. This increase of the charge trapping density in the interfaces is the key factor for the increase of the total charge trapping capability of the devices. As the number of the inter-diffusion layer increases, the charge trapping capability of the RTA samples improves significantly. Especially for5L-RTA sample, when compared with the as-deposited samples, the total charge trapping merit increases by about60%, indicating that increasing the number of the interfaces with strong inter-diffusion is an effective approach to create more traps in the charge trapping layer with consistent thickness. Increasing the number of Al2O3intercalation layers can also suppress the tunneling of the trapped charges back to Si substrate, and enhance the retention characteristics of the devices. The first-principle calculations results prove that additional trap sites can be created by the inter-diffusion of HfO2and Al2O3. Enhancing the inter-diffusion can create more traps in the interface, and then improve the charge trapping capability of the devices.3. Based on the experiments that traps can be created by the inter-diffusion and then improve the charge trapping capability, high-k composite oxide such as HfAlO was chosen as the charge trapping layer to further improve the charge trapping capability. The results show that the device with the HfAlO charge trapping layer has better charge trapping capability than that of HfO2/Al2O3multilayered memory devices. For the HfAlO thin film deposited by ALD, thermal treatment can make HfO2and Al2O3mixing more evenly, and enlarge the inter-diffusion of the two materials. In this case, more traps can be created in the HfAlO film, and then improve the charge trapping capability. When the sweeping gate voltage was±12V, the device had a large memory window of6.29V. Meanwhile, the device with HfAlO charge trapping layer exhibits fast program/erase speed and good retention performance, indicating that the memory device with high-k composite oxide charge trapping layer could be a promising candidate for future memory applications. |
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