Research On High-density Charge Trapping Nonvolatile Memories

As the market requests nonvolatile flash memory with increasingly high-density and large-capacity, flash process technology goes into 1X nm node. Consequently, the reliability of tranditional floating-gate flash memory decreases because of its structure limitation on scaling down and cell-to-cell interference, so charge trapping memory(CTM) becomes a potential substitution. Three methods are proposed to improve the storage density of CTM: using multi-level cell(MLC) or multi-bit cell(MBC) technology to increase the number of stored bits in a single memory device; employing high-k materials as charge trapping layer to enlarge memory window; changing the planar device to 3D structure to reduce the equivalent area of memory cell. This thesis mainly investigates high-k material application in flash memory and reliability issues related to 3D memory device, and also studies the methods to realize high-density embedded flash.High-k materials as charge trapping layer in flash memory are investigated, including device structure, process technology and energy band optimization. By comparising the performance of single layer Ta2O5, Hf O2 and multilayer Ta2O5/Hf O2/Ta2O5(THT), Hf O2/Ta2O5/Hf O2( HTH) structure, we find multilayer structures can achieve better program and erase characteristics. The energy barrier exsiting in THT lowers the efficiency of trapping and emitting charge in 2nd Ta2O5 layer(next to blocking oxide), so HTH is better for memory application than THT. Furthermore, the process technology to produce MAHTHOS(Al-Al2O3-Hf O2-Ta2O5-Hf O2-Si O2-Si) is optimized. The results indicate high temperature annealing improves the program/erase speed, and O2 atmoshpere annealing lowers the back tunneling injection. Finally, the thicknesses of the two Hf O2 layers in HTH structure are regulated to improve the performance of MAHTHOS device, achieving large memory window and good reliability, which can be used in MLC technology.For 3D CTM, charge may migrate along the vertical continuous nitride, inducing interference between neighbouring cells and restriction on scaling down of vertical memory strings. This thesis proposes and verifies a methodology to extract the effect of charge lateral migration from retention characteristics. Moreover, based on this method, mechanisms of charge lateral migration are analyzed by new models, incorporating the effect of charge spacial profile and charge energy profile to the lateral migration. Experimental and simulation results indicate that Poole-Frenkel emission contributes mainly to the charge lateral migration, and trap-to-trap tunneling can be ignored. Based on the verified models, the effects of nitride thickness and stress induced degradation to lateral migration are further studied.For embedded flash field, based on a two-bit nonuniform-channel CTM, we propose an e NAND and e NOR mixed array architecture, and discuss its operation methods. Meanwhile, by simulation and experiment, we investigate the method to design peripheral circuits system for high-density and large-capacity memory array. A 1 Gb NOR flash is implemented successfully with a random read speed of 100 ns per bit.