| SONOS charge-trapping memory devices have been widely used in digital cameras, cell phones and other portable devices due to its low operation voltage, fast program/erase(P/E) speed, good endurance performance and long retention. As the integration of semiconductor industry is increasing, the traditional SONOS type charge-trapping memory device is unable to meet the demands of higher storage capacity, faster P/E speed, lower consumption and longer retention. Nanocrystal memory device has been considered as a promising candidate to replace conventional SONOS type memories due to its high storage capacity, fast P/E speed and low operation voltage. Nanocrystal(NC) memory devices are very stable against the source or drain disturbances. The leakage current induced by stress is negligibly due to discrete charge storage. However, it is a big challenge for the charge trapping memory devices to show good performance at 10-years retention characteristic due to the ultra-thin tunneling layer. Also, the low charge trapping efficiency is the crucial problem for nanoscale charge trapping memory devices. Employing high-k materials to replace traditional Si3N4 can significantly improve the charge trapping efficiency and the retention property of NCs memory devices. Whether the charge storage in NCs-based memory devices should be ascribed to a bulk trapping or an interface trapping is not yet clear. For a charge-trapping memory device, the charge-trapping layer with high charge-trapping capability in a small scale is critically important for the further application in the future. New devices derived from SONOS type memory device have been proposed to improve the charge-trapping ability and reliability, such as the multilayered charge-trapping memory devices, including HfO2/ZrO2/HfO2 and HfO2/Al2O3/HfO2, etc. which show wonderful charge storage and retention properties as compared with those memory devices with single charge-trapping layer. Although the charge-trapping mechanism in the memory device with multilayered high-k oxides as the charge-trapping dielectrics is quite complicated, we found some definite evidences that the charge-trapping behaviors in these multilayered memory devices should be ascribed to the inter-diffusion at the interface of different high-k oxides. So it is sensible to increase the charge-trapping density by mixing different high-k oxides completely. The charge-trapping memory devices were always undertaken a rapidly thermal annealing treatment (RTA) at very high temperature. However, CU2O as a high-k oxide has a low crystalline temperature which is lower than 200℃, so the memory device with Cu2O do not need to suffer the high temperature RTA process, which could reduce the diffusion of Cu. In this dissertation, we have designed a new type of charge-trapping devices based on Al2O3-Cu2O(CAO) composite and investigated their properties systematically.In this dissertation, the charge-trapping efficiency, microstructure and endurance of the charge-trapping devices based on Al2O3-Cu2O(CAO) composite have been studied systematically. The effects of the composition of the charge-trapping layer, rapid thermal annealing (RTA) temperature and tunneling layer thickness on the properties of the memory devices were also studied. The main results are summarized as followed:1. The composite with a composition of Al2O3:Cu2O=0.5:0.5 was used as the charge-trapping layer. Al2O3 tunneling layer and blocking layers were deposited by using atomic layer deposition technique. The rf-magnetron sputtering technique was used to deposit CAO charge-trapping layer. It was observed that the charge-trapping memory device based on CAO composite show large charge storage capacity, fast P/E speed and long retention. The analysis on the cross-section morphology of the memory device by using high-resolution transmission electron microscopy(HRTEM indicates that CU2O nanocrystals precipitate from the super-saturated parent CAO after RTA at 200℃ 。The charge-trapping efficiency of the memory devices based on CAO composite was very strong. At a working voltage of±11V, a memory window of 9.22V was obtained. The X-ray photoelectron spectroscopic (XPS) study shows a shoulder from Cu2+ions around the peak of Cu1+ions. It was suggested that the charge-trapping mechanism should be attributed to the defect states formed by the inter-diffusion of two oxides. The memory device would be turn on under the pulse with amplitude of 10 V and a pulse width of 10-2 s. The memory window did not degrade significantly after P/E for 105 times.2. The effects of different compositions of Al2O3-CU2O composite in the charge-trapping memory devices on the charge-trapping efficiency, P/E speed, endurance and retention properties were investigated systematically. Three samples with same thickness and different mole ratios of Al2O3:Cu2O(0.9:0.1,0.7:0.3 and 0.5:0.5, respectively) were synthesized. It was observed that under the same sweeping voltage, the charge-trapping density increases significantly as the increase of CU2O component. The effective inter-diffusion between Al2O3 and CU2O in the CAO charge-trapping layer with more CU2O is higher, which leads to a larger charge-trapping capability. The analysis on the cross-section of the memory devices by using HRTEM shows that Cu2O in the device with a molar ratio of Al2O3:Cu2O=0.9:0.1 was totally’molten’ in Al2O3, so it doesn’t precipitate from the parent CAO matrix after RTA at 200℃. As the increase of Cu2O composition, some CU2O nanocrystals precipitate from the super-saturated parent CAO matrix after RTA at 200℃. The precipitation of Cu2O would seriously harm the stability of the memory devices, so the CAO composite with low Cu2O composition shoud be used as the charge-trapping material. The XPS study shows that part of Cu1+ions was oxidized to Cu2+. The molar ratio of Cu2+/Cu1+decreases as the increase of Cu2O composition. The Cu2O composition shows no direct effect on the P/E speed and endurance performance of CAO memories, while the device with a higher Cu2O composition shows a better retention property.3. The effects of different RTA temperatures on the charge-trapping properties of CAO memory devices were investigated systematically. The target with a molar ratio of Al2O3:Cu2O=0.9:0.1 was used to deposit the charge-trapping layer by using rf-magnetron sputtering technique. The RTA treatment at 200℃,250℃,300℃ were completed before the deposition of the blocking layer. It is observed that under the same sweeping voltage, the charge-trapping density decreases significantly as the increase of RTA temperature. The analysis on the cross-section of memory devices by using HRTEM shows that CU2O doesn’t precipitate from the parent CAO matrix after RTA at 200℃. The charge-trapping efficiency in this case is better than that in other case due to the more inter-diffusion between Al2O3 and CU2O. Some CU2O nanocrystals precipitate from the super-saturated parent CAO matrix when the RTA temperature is 250℃. The effective inter-diffusion between Al2O3 and CU2O would be reduced due to CU2O precipitation. As the RTA temperature increased to 300℃, the effective inter-diffusion between Al2O3 and CU2O is further reduced due to more CU2O precipitation. So the charge-trapping density of the device annealed at 300℃ was the lowest. It proved that the charges trapped in CAO charge-trapping memory devices should not be related to bulk Cu2O, but to the interface of CU2O/Al2O3. The XPS study shows that part of Cu1+ ions was oxidized to Cu2+. The molar ratio of Cu2+/Cu1+decreases as the increase of RTA temperature. The RTA temperature shows no direct effect on the P/E speed of CAO memories. The retention properties of CAO memory devices would be slightly improved after annealed at a higher RTA temperature, while a higher TRA temperature would lead to the bad endurance performance. A RTA temperature of 200℃ was the best choice for CAO charge-trapping memory devices.4. The effects of the thickness of the tunneling layer on the charge-trapping efficiency, P/E speed, endurance and retention properties were investigated systematically. SiO2 was used as the tunneling layer. Three kinds of the CAO charge-trapping memory devices in which the tunneling layer has a thickness of 2nm,3nm and 4nm were fabricated, respectively. The target with a molar ratio of Al2O3:Cu2O=0.5:0.5 was used to deposit the charge-trapping layer by using rf-magnetron sputtering technique. The result shows that the memory device with a 2-nm tunneling layer has a very small memory window because the trapped charge may tunnels back to the Si channel. The memory window of the memory device would be larger if we increase the thickness of the tunneling layer. By comparing three kinds of the memory devices, we conclude that thickness of the tunneling layer of the charge-trapping memories based on CAO composite should be larger than 3 nm. |
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