Charge-Trapping MONOS Memory With High-k Stacked Gate Dielectrics

As next-generation application of the traditional floating-gate flash memory, charge-trapping memory presently faces some severe technique challenges as the technology node continuously scales down, i.e. at low operating voltages, large memory window, fast program/erase (P/E) speed, good endurance and10-year data retention must be attained. For metal-oxide-nitride-oxide-silicon (MONOS) memory, the conventional SiO2and Si3N4are substituted by the high-k dielectrics, and hence optimization of the material, structure and fabricating processes of its blocking layer (BL), charge storage layer (CSL) and tunneling layer (TL) will be the main approach of improving performances of charge-trapping memory. These are just research work performed in this dissertation. Experimentally, some high-k dielectric materials as CSL are investigated and compared, the novel dual-CSL and dual-TL structures of high-k/low-k are designed and prepared, and optimization of the fabrication processes has been carried out to achieve a good trade-off among the memory window, P/E speed, endurance property and retention characteristics. Theoretically, the electron-retention model of MONOS memory under the programming state has been established.Some investigations have been done on the high-k dielectric materials and fabricating processes of the CSL:①The La-based binary-mixing oxides as the CSL of MONOS memory are prepared by doping Hf, or Ti, or Y into La oxide and their effects on the performances of the devices are investigated and compared in detail. It is experimentally found that high density of traps with deeper levels and thus high trapping efficiency, strong Hf-N and La-N bonds and stable HfLaON/SiO2interface and thus reasonable data retention can be achieved by incorporation of N into HfLaO to form HfLaON. Compared to devices with LaTiO CSL, the devices with LaYO CSL exhibits larger memory window, higher program speed, better retention and endurance properties, suggesting that the Y-doped La oxide could provide a large amount of bulk traps and thus high charge-trapping efficiency, and effectively suppress formation of the interfacial silicate layer near the CSL/SiO2interface during post-deposition anneal, reducing generation of shallow-level traps or defects;②Using GdO as CSL, the effects of different sputtering ambient (N2or O2) and anneal processing on quality of GdO thin film and performances of the memory are investigated. Experimental results indicate that the memory window is greatly increased due to generation of a large quantity of electron traps induced by incorporation of N into the GdO dielectric, and furthermore, a good trade-off among the memory window, P/E speed, endurance, and retention characteristics can be achieved by NH3annealing at550℃for2min, which can effectively suppress creation of shallow-level traps near the CSL/SiO2interface, and thus give suitable spatial distribution of traps with deeper energy level in the bulk of the CSL.Regarding novel stacked gate structure:①A stacked gate structure of Au/HfAlO/AlN/(HfON/SiO2)/Si is proposed and prepared by in-situ sputtering method, where the ultrathin dual-TL of HfON/SiO2is used to increase speed and efficiency of charge injection, the AlN CSL with deep-level traps is employed to provide large memory window, good charge capturing capability and stability of charge trapping, Au electrode with high work function and HfAlO BL with suitable k value and barrier height can effectively reduce electron injection from the control gate into CSL during erasing and leakage of those charges in CSL during retention, thus shortening erase time and enhancing data retention.②Based on bandgap engineering, a dual CSL composed of TiON/HfON is proposed and prepared, and a tapered bandgap structure with bandgap increasing from the TL to the BL is formed due to the inter-diffusion between Ti and Hf near the TiON/HfON interface which leads to an intermixing layer of HfxTiyON with varying Hf/Ti ratio in the dual CSL during post-deposition annealing. A large quantity of electron traps exists in the dual CSL due to the mixing of HfON and TiON. The tapered bandgap structure can give a multi-level trap distribution, which is beneficial for enhancing charge capturing capability of traps and charge injection efficiency, thus obtaining large memory window and high P/E speed. In addition, a large barrier height between the TiON and TL can effectively block escaping of those trapping charges, enhancing data retention.Theoretically, an analytical model of electron retention under the programming state is established by taking trap-to-band (TB) tunneling as leakage mechanism of the trapped electrons, assuming a triangle-like energy-level distribution of traps and considering the trap spatial distribution as the uniform or local profiles respectively. The correctness and accuracy of the model are confirmed by good agreement of the simulated results with experimental data.