Study On Tunneling Layer And Charge Storage Layer Of Charge-Trapping Memory

Metal-Oxide-Nitride-Oxide-Silicon (MONOS) memory are facing crucial challenges on improving the performances (e.g. memory window and program/erase speed) and reliability (e.g. endurance and retention characteristics) under low operation voltages. The main solution to this problem is to employ suitable high-k materials in tunnel layer, charge storage layer, and blocking layer, and optimize fabrication processes and device structures, which are just tasks of this thesis. Experimentally, influences of different materials, fabrication processes and structures of the tunnel layer and different high-k materials as the charge storage layer on memory performances are investigated, and the processing conditions are optimized to achieve a good trade-off among memory window, program/erase speed, endurance and retention properties. Theoretically, a program model is established for the MONOS memory, which can well match the experimental results under a large range of programming voltages.Work on materials, fabrication processes and structures of tunnel layer are as following:①oxide/oxynitrides are respectively grown in O2, N2O and NO ambients to use as tunnel layer and their effects on memory performances are investigated and compared. The experimental results reveal that the device with oxynitride grown in NO ambient as tunnel layer exhibits larger memory window and faster program/erase speed. This is attributed to the fact that the strong nitridation ability of NO induces more nitrogen incorporation, giving rise to reduction of electron barrier height between the oxynitride and Si substrate, thus enhancing the electron-injection efficiency. Also, the device has good endurance and post-cycling retention characteristics, which is ascribed to formation of more strong Si-N bonds at/near the oxynitride/Si substrate.②Starting from the barrier engineering of the tunnel layer, a stacked low-k/high-k of SiO2/TaON as tunnel layer is proposed and fabricated. The experimental results show that the device with SiO2/TaON as dual tunnel layer has better performances, i.e. larger memory window, faster program/erase speed and better endurance properties compared with the device with SiO2/HfON or single SiO2as tunnel layer. This is due to the fact that TaON has larger dielectric constant, smaller band offset to Si substrate, and better interface quality with SiO2. In addition, compared with the single SiO2tunnel layer, the retention of the device with dual tunnel layer has significantly been improved.Work on high-k materials and fabrication process for charge storage layer are as following:①ZrO2and ZrON are employed as charge storage layer respectively, and the effects of nitrogen incorporation on memory performances are investigated. The experimental results show that the device with nitrogen-incorporated charge storage layer (ZrON) has better memory performances. This is due to the fact that formation of Zr silicate can effectively be suppressed by nitrogen incorporation, improving interface quality between ZrON and SiO2, and thus increasing dielectric constant. In addition, the trap density in the charge storage layer is increased by incorporating nitrogen into the metal oxide, which is beneficial for the increase of memory window.②HfTiON is used as charge storage layer, and effects of the Ti content on the memory performance are thoroughly investigated. The constant-current stress measurement reveals that the carrier-injection efficiency and charge-trapping efficiency are enhanced as Ti content increases, resulting in larger memory window and faster program/erase speed. However, microanalyses indicate that a Ti-silicate layer at/near HfTiON/SiO2can be formed when Ti content is excessive, which will deteriorate the data retention. Therefore, the Ti content in the HfTiON film needs to be optimized to achieve a good trade-off between the program/erase and retention properties. In this work, the MONOS memory with a Hf/Ti ratio of～1:1in the HfTiON film exhibits a large memory window, high program/erase speed, good data retention and endurance properties.For the modeling and simulation, starting from the physical processes of the MONOS memory device under programming condition, a simplified program model is established by using effective capture cross section as a fitting parameter. The simulated results are compared with the experimental results to verify the correctness and validity of the model, and extract the effective capture cross section under different programming voltages.