The Studies On The Application Of High-k Dielectrics In The Charge-trapping Memory Devices

With the development of semiconductor technologies, the scales of the semiconductor memory device are shortened continuously. When the characteristic scale is close to the technological node of 22nm, the traditional floating-gate semiconductor memory will approach its physical and technological limits. Developing non-volatile semiconductor with high data storage density, high programing/erasing speed and low power dissipation becomes the research focus. As a new kind of non-volatile semiconductor memory device, the charge-trapping memory device, which is well compatible with traditional CMOS technology, needs less shadow mask and is of low cost, is believed to replace the traditional floating-gate memory device. Of the charge-trapping memory devices, SONOS （polysilicon-oxide-nitride-oxide-silicon） type charge-trapping memory device with low power dissipation, fast programing/erasing speed and good endurance property has been studied widespread.Due to the replacement of polysilicon by Si₃N₄ in traditional floating-gate memory device, the capability of data storage in SONOS type memory device has been improved. The retention property will deteriorate with the decrease of the thickness of Si₃N₄ layer. It is reported that the replacement of Si₃N₄ by high-k dielectric in SONOS type memory device can improve its ability of further scaling-down and its charge-trapping efficiency.The memory properties of a high-k multilayer-structured charge-trapping memory device and a high-k composite charge-trapping memory device were studied in the thesis, and the effect of defects on the charge-trapping capability of the memory structure were investigated by using the first principle theoretical calculation. Finally, the physical parameters affecting the performance of high-k composite charge-trapping memory device were studied systematically. The main achievements are followed: A multilayer-structured high-k charge-trapping memory prototypical device was fabricated:SisN₄ or high-k dielectric layer in traditional SONOS type charge-trapping memory device was replaced by TiO2/Al₂O₃ multilayers. To investigate the effect of the oxide interface on the memory properties, some memory devices with the same thickness of the charge-trapping layer but with different number of intercalation layer of Al₂O₃ were fabricated. It was observed that with the increase of the interface, the memory window of the as-deposited memory devices increases gradually, indicating that the oxide interfaces in the charge-trapping layer play an important role in improving the charge-trapping efficiency. The memory window of the as-deposited memory device with 5 interfaces TiO₂/Al₂O₃ is about 9.72V, and a degradation of 29% in its initial stored charges after 10 years was observed.A memory structure p-Si/Al₂O₃/TAO-91/Al₂O₃/Pt was fabricated by using atomic layer deposition and magnet sputtering techniques, and the density of stored charges under an applied voltage ±11 V is about 1.29×1013/cm2. It was observed that the memory window of the as-deposited memory structure almost show no degradation after 1 x 105 programming/erasing cycles, and the memory window after 104s for a memory device under a programming or erasing operation degrades about 35%. The electronic structure of Al₂O₃ with Ti and oxygen vacancy was calculated by using the first principle theoretical method, and it shows that the defect states can be produced by the inter-diffusion between TiO₂ and Al₂O₃:more serious inter-diffusion, then more defect states.Three kinds of high-k composite charge-trapping memory devices with three relative compositions between Ta₂O₅ and Al₂O₃ were fabricated. Under an applied voltage ±11V, the memory device with a composition （Ta₂O₅）_0.5（Al₂O₃）_0.5 shows a memory window 7.39V, and a density of stored charges 1.97×1013/cm2. （Ta₂O₅）_0.5（Al₂O₃）_0.5 memory device shows a largest memory window due to the most effective inter-diffusion between Ta₂O₅ and Al₂O₃, thus a largest density of stored charges. （Ta₂O₅）_0.5（Al₂O₃）_0.5 memory device also shows largest programming/erasing speed, in accordance with its special band alignment with Si substrate. The potential difference between the bottom of the conduction band of （Ta₂O₅）_0.5（Al₂O₃）_0.5 and that of Si substrate is smallest among three memory devices.