Manufacturability Research And Design For Deep Submicron VLSI

With the rapid development of IC manufacturability process, the integrity of IChas been rising rapidly, the process steps are becoming more and more complex, andthe dimension of the process is shrinking. IC design for manufacturability (DFM)which aims to directly enhance the yield of IC and reduce the cost of the die, it hasbeen into the notice of the IC industry.This thesis has done some research on the design for manufacturability in deepsubmicron VLSI. First, the IC manufacturability process is briefly introduced in thiswork followed by the analysis of the process variability, lithography problems,chemical mechanical polishing problem and the antenna effect in deep sub-micronfabrication process. Second, the mechanism of IC yield loss is expounded, whichconsists of three parts including the random yield loss, the yield loss caused by systemerror and the yield loss caused by parameter fluctuation.To solve the problems caused by the IC manufacturability, basing on that ICdesign and manufacture are mutually coordinated and interrelated, this thesis putsforward the corresponding design for manufacturability and adds the DFM in thephysical design as well. In this work, the methods of using the dummy filler, doublevia and wider metal slotting are used to solve the chemical mechanical polishingproblem, while the methods of jumpping or inserting diodes are used to solve theantenna effect; and the global routing DFM is also used to wire spread in the physicaldesign stage. Finally, the way of using on chip variation (OCV) model to check thetiming in the sign off stage is also proposed.After putting forward the design for manufacturability, a physical design flowadding DFM based on the traditional physical design is proposed in this thesis. Inaddition, this work takes the example of the smart card reader chip designed byBeijing embeded system key lab, adds DFM to the physcial design of smart cardreader chips and completes the design of the chip. The yield problems are solved infabrication process through the implementation of DFM. Finally this chip issuccessfully taped out in SMIC0.18um process.Through the research on the design for manufacturability in deep submicronVLSI, this thesis has proposed a physical design flow adding DFM. Adding DFM tothe traditional physical design can reduce the chance of making errors in the processof IC manufacturing as well as the yield loss in IC fabrication process. This thesisprovides some reference for the future research and design for manufacturability ofdeep submicron VLSI.