Manufacturability Design (dfm) Is The Key To The Analysis Of The Pattern Matching Method And Practice

Since fist Integrated Circuit (IC) generated in 1958, the IC has been developing at very high speed; the complexity for minimum component cost has increased at a rate of roughly a factor of two per year. According to history of IC, the Characteristic size has decreased 30% in each generation.As semiconductor industry marching through 0. 13um, 90nm, 65nm and even smaller technology nodes, yield loss has become an increasingly serious issue for the semiconductor manufacturers. How to quickly ramping up the yield is one of the biggest challenges faced by today’s nanometer level semiconductor manufacturers. The adoption of complex state-of-the-art design technology further complicates the issue.The first step in improving the yield is to understand the cause of the yield loss. There are many causes for the yield loss. Some of the common causes for the yield loss are incorrect operation of manufacturing equipment, design defects, and incorrect application of Resolution Enhancement Techniques (RET). In short, there many causes for the yield lost. We name them Critical Pattern. Some of them are random defects, which can be avoided by strict management and correct RET. Some of them are systematic defects, which come from circuit layout itself. For Volume Yield Diagnostics (VYD), the main concerns are on the systematic defects which caused by pattern, since they are more numerous, and tougher to resolve. Wafer inspector can scan the wafer point by point, and it can find and report the defects. The analyzer needs to analysis each defect. For most systematic defects which caused by pattern will not fail 100 percent, it’s more difficult to tell if the defect is or is not systematic defect which caused by certain problematic pattern. It can be confirmed only after collecting these patterns and generating special test wafer under different operation conditions. This method costs much. To find the pattern fast, and give the location list to the wafer inspector to scan them one by one, this is cheaper and reasonable. To some known systematic defect which is caused by certain problematic patterns which are correctable, an important task of VYD is how to accurately characterize them and quickly locate them in a given design.As the request of critical pattern searching, the research of this thesis focuses on following items.1. Talk about pattern definition method base on the shape of critical pattern.2. Solve complex 2D with multi-layers pattern searching issue, and improve the performance of pattern searching method.3. Integrate the pattern matching method into some related wafer inspector device, and improve the performance of the device.This thesis presents a whole method to define the pattern, the description method come from polygon shape directly. The method developed in this thesis research can binding with wafer inspector device, it is possible to analysis inspecting pattern on line to improve run speed of inspector device. And, this thesis solved questions about how to define and search 2D patterns which are difficult to solve in current EDA pattern search method, also solved questions about how to define and search more complex 2D with multi-layers, and even improved the search performance.To each method, a sort of description language is needed. To full polygons searching method, here use Angle-segment Sequence description language. To incomplete polygons searching method, here use a new data structure to descript it, which is called edge structure. The edge structure can be reused, also can be combined and split, even can be used for a part of polygon segment matching. The edge structure combines the description in math function and computer technology, which make a big progress in data searching, data matching, and accuracy. To these pattern description language and data structure, this thesis gives a detail introduction and analysis, includes the difference in using.This thesis presents research and implementation on the methods for characterizing the critical patterns, to search using a set of defining parameters, and to search using pattern match method. For complex pattern, distinction needs to be made as to whether a critical pattern contains a full polygon, multiple full polygons or only incomplete polygons. A major part of this research is on the most efficient pattern match techniques for these three different kinds of complex critical patterns.In the compute program developed as the result of this research, the relevant data about the complex critical patterns to be searched are required. The program will then search the instances of these complex critical patterns with a given design using the pattern match techniques developed in this research. This can help designer to find the Critical Pattern fast to improve yield. At same time, this research can catch the lower sensitive area as the requests of layout inspector device by parameter setting, the inspector device can skip or enlarge the parameter setting to avoid false defect pattern catching, which may give the overload job to yield analysis, also which may increase the cost of device. These methods have been integrated into some EDA tool and some related inspector device, and which is a core part of the EDA tool and the device. The run speed is very fast, it reaches the goal as expected.