Study On The Simulation And Optimization Methods Of Functional Yield Of Integrated Circuits

This dissertation aims at discussing the model, simulation and optimization methods of functional yield of integrated circuits. The Author抯 main contributions are as following: First, the principle of circuit faults caused by manufacturing defects is studied. Some manufacturing defects that have the most significant influence upon functional yield, such as extra material defects, missing material defects and dielectric pinhole defects, are discussed to obtain the corresponding geometrical abstractions. Then a fault recognition algorithm and the critical area extraction method of dielectric pinhole defects are presented. Second, fault recognition is one of the kernel techniques of a functional yield simulation system. In this dissertation, corresponding fault recognition algorithms are proposed according to different defect types. Due to the complexity of layout, whether a defect causes circuit faults or not is determined by the size, position of the defect and the surrounding layout geometry. So the actual geometry net of local layout must be extracted to avoid such a misrecognition case as an extra material defect touches two or more neighboring conductors within a same electrical net. As a result, effective rules to recognize defect-induced faults are presented to recognize primary fault patterns, such as circuit short faults caused by extra material defects, line open faults caused by missing material defects and circuit short faults between neighboring layers caused by dielectric pinhole defects. After combining research results of defects model, negative binomial random number generation, CIF layout decoding, fault-recognition and Monte Carlo functional yield simulation methodology, a functional yield simulation system is developed. With its graphics user interface and interactive operations, the simulation system can be applied to obtain the functional yield of an integrated circuiU by analyzing its many defect modes and defect sensitive layers. With the simulation results of a metal test structure layout and a terminal interface chip XT- 1, the simulation system is checked. Then, the available critical area extraction model and its disadvantages are studied and an improved critical area extraction model is presented in this dissertation. The improved model performs a good accuracy in critical area extraction for general layout geomeity. Especially, geometry net of local layout is taken into account to derive the efficient critical area extraction algorithms of extra material defects. A grouping-sorting technique is also developed to improve the computation efficiency of short critical area extraction. Therefore, different critical area extraction algorithms ar~ developed according to diffem~f defect tvnes~ With the concept of critical area, the unitarity of Monte Carlo method and critical area method is discussed in fault-sensitivity analysis. Finally, optimization design techniques for functional yield enhancement are studied in this dissertation. By comparison of yield optimization methodologies, the geometry adjustment method of local layout is proved suitable to improve functional yield without increasing chip area. Based on the criterion of sub-block fault-sensitivities of layout, the optimization selection problem of layout sub-blocks is solved. Applying the Monte Carlo fault-sensitivity analysis method to layout sub-blocks, the disadvantages of critical area extraction in local layout geometry are elimi...