Research Of Key Techniques On Front End Of A DMB Receiver System

The fifth media—Digital Multimedia Broadcast(DMB) has already become one of the fastest developing hot point in the field of information science for its capability of providing various kinds of multimedia information such as audio, video, text and image. DMB system consists of antenna, receiver, baseband audio/vedio decoder and encrypting system. Among them, receiver is the key hardware to realize receiving of feeble broadcasting signals for post digiatal process. Meanwile, low coast requirement make the designers of receiver IC using Si CMOS process instead of GaAs. But the development of CMOS process primarily aims at the optimization of digital circuits, resulting in low transconductance and large noise for MOS device. Therefore, in order to realize RF analog front end of the receiver system, it need to break through the physical bases and key techneques.In this dissertation, modeling of integrated inductor, theory and structure study on key blocks such as RF LNA and VGA, ADC/DAC, design of critical unit circuits, are performed to realize the physical IP design and integration of mobile receiver system that meets the China standard of DTMB and CMMB.1. Based on the theory of electromagnetic field, this dissertation makes a detailed analysis on the causes and distribution characteristics of the high frequency parasitic effects of integrated inductor, such as proximity effect, skin effect and eddy current losses in the substrate. Through simplifying partial equivalent element circuit methodology properly, I-V equation of inductor is derived and the expressions for series resistance Rs(f) and effective inductance Ls(f) are presented. The calculation accuracy and efficiency of the model presented in this dissertation is verified in comparing simulation. Simulation results also show that Si substrate with low resistivity is a severe restriction for the design of CMOS RFIC.2. Based on the analysis of existing structures, final LNA and VGA circuits are designed and optimized. Among the two critical units, inter-stage inductor is added to cascode LNA structure, resulting a gain increased to 18.2dB, and the noise factor decreased to 1.6dB; resistors are replaced by active loads and Miller Effect restraint transistor is also introduced to increase bandwidth in VGA, additionally, exponentially controlled approximation function is constructed. Gain control range of the designed VGA is greater than 60dB, and the gain changes linearly with the control current of DAC in the range of 14dB~78dB with error less than±1dB. Such performances of the VGA satisfy the need of gain adjustment under radio frequency. Current-voltage conversion circuit is omitted because the VGA is directly controlled by the output current of DAC, thus reducing the area.3. Error sources and statistical parameters such as the mean value, variance of INL of a segmented current-steering DAC are analyzed systematically. The index INL is modeled based on random theory and the process of Brown Motion. The model is verified in terms of yield, and optimization suggestions on segment ratio in current steering DAC are also presented.Meanwile, this dissertation presents a high precision high PSSRR bandgap current reference compensated by the plus and minus temperature coefficients of resistors with feedback to restrain the ripple on power supply, a modified cascode unit current source to obtain high output resistense and low glitch, and a rapid low glitch switch driver with the function of clamping and higher cross points. Finished final DAC layout according to the design rule of 0.35μm Si CMOS process.4. Combining the advantages of Flash, Pipeline and SAR structures. This dissertation presents a novel segmented multi-division search algorithm A/D conversion scheme. Due to the novel A/D conversion scheme, not only the number of comparators is dramatically reduced, MDACs and residual amplification module RAs which are essential in traditional multi-step ADC and Pipeline ADC are also omitted, thus reducing the power consumption and area efficiently. This dissertation also presents the optimized search algorithm, demonstrating the optimized selection method for stage accuracy according to whether the resolution of the ADC can be partitioned equally. Based on the principle of this scheme, a 3+3+4 mixed mode ADC structure combined segmented multi-division search algorithm with pipeline is designed.Through the analysis of step response of two order system and derivation of transfer function, a novel compensation method is presented. Application of the method on the design of a folded cascaded amplifier show that the settling time of the opamp is reduced from 5.08ns to 3.89ns, or 23.4%. Simulation result verifies the efficiency of this method.5. Completed layout of the ADC is finished according to the design rule of 0.35μm Si CMOS process. Based on the design principles of high speed high precision mixed signal IC layout, some important factors such as interference of digital circuits to analog circuits, error distribution of the process, symmetry of differential signals and some practical situations of the process are comprehensively considered. Additionally, placement and routing skills such as ground line shielding and symmetrical matching are applied. Final size of the layout is 1534μm×2172μm. After extracting the parasitic resistor, capacitor and device parameters with Calibre PEX, HSpice simulator is used to post simulate the circuit. Post simulation results show that DNL of the ADC is smaller than±0.5LSB, INL is smaller than±1LSB, SFDR is 72.4dB, and the total power consumption is 215mW, indicating that the accuracy of the ADC achieves 10bit resolution. Thus the success of tape out is guaranteed.Look forward to the future, it should be noted that contimuous deeper researches and developments are still expected on system architechture, RF device model, low-power data converter and monolithic involved in mobile digital multimedia broadcoasting receiver.