Study Of Nanocrystal And High-k Materials For Floating Gate Memories

IC industry has seen the rapid growth of flash memory market recently, owing to the extensive demand of 3C electronics, such as notebooks, smart phones, digital cameras, etc.. However, requirements of long-rention, low-power, high-speed, high-density flash bring greater challenges when critical dimension (CD) scales into the sub 100nm and nm regime. This dissertation is mainly to address the issues on how to improve the storage performance.First, advanced Sentaurus TCAD tool is employed to simulate the performance of sub-100nm NOR cell and SONOS. To increase the storage density, monodispersed Au nanoparticles are synthesized through chemical route. Then they are deposited onto the surface of tunneling oxide by spin-coating method to form ordered array, which are used as storage node. The surface topography shows that high density, ordered nanoparticle array has been realized, while the electrical measurements indicate good storage characteristics. To improve the data retention, Ge/Si hetero-nanocrystal based hetero-double barriers, act as tunneling oxide and storage nodes, instead of conventional monotypic nanocrystals. According to the electrical characteristics, better data retention could be achieved, especially for hole storage. Finally, high-k materials and multilevel Cell(MLC) structure are imported. High-k materials are essential candidates to take place of SiO2 as tunneling oxide or control oxide, since they're beneficial to achieve lower current leakeage and longer data retention.The significant achievements from our research, focusing on storage node materials, device structure and high-k materials, will promote the technical development and the innovation of nanocrystal floating gate flash memory devices.