Design And Realization Of Large Capacity Radiation Hardened PROM With RHBD Technologies

This thesis is based on the “Large Capacity Radiation Hardened PROM” project developed by Shenzhen State Microelectronics Company. As a key component of the manned space project, satellite computer system and weapons system, the anti-radiation of large capacity radiation hardened memory directly affects the reliability of the whole system. By comparing the anti-radiation performance between the different structural memories, the single-transistor-memory with anti-fuse was chosen as the basic unit of the memory as its good anti-radiation perfermance. In the following part, the mechanisms of different kinds of memories and large capacity PROM memories are studied. In a word, the whole circuit is designed successfully.This thesis focuses on design method of radiation hardened device, radiation mechanism, Single event effect TCAD software modeling and radiation hardened verification at circuit leve. Furthermore, the function of radiation in integrated circuit and the mechanism of radiation hardened device are discussed.The single event effect on MOS transistor is simulated using TCAD software. By changing the condations, a series of current pluses are obtained. In the analysis of the influence of several important factors, such as the size-varied NMOS transistors, the different LET values, the incidence location and angles on the SET pulse width and magnitude are executed. In the end, a PWL transient pulse current simulation model under single even effect is established.In this project, system level, circuit level and process level design for radiation hardened are realized respectively. Radiation hardening realized using memory redundancy and EDAC technology in the system level. Circuit level radiation hardening design mainly adopts four methods, namely, triple modular redundancy reinforcement design, time redundancy reinforcement design, C unit reinforcement design and Dual Interlock Cell structure. Moreover, resistance and coupling capacitor are introduced in the circuit critical nodes in the whole design. Process-level reinforcement mainly employs proper layout design rules and processes to enhance the anti-radiation performance.In order to verify the effect of radiation hardened circuits, circuit-level simulation techniques are testified according to the PWL transient pulse current model. A comparison between the simulation of reinforced and unreinforced circuit is carried out to verify the radiation hardened project. Lastly, pre-simulation and post-simulation are employed to the whole chip system. The chip tests and chip irradiation experiments show that the design indicators of the circuit and anti-irradiation indicators in this project meet requirements. The design capacity is 16 Mbit. The capacity of Single Event Latchup(SEL) of LET is 75 Mev·cm 2/mg. The SEU error rate is less than 1x10-10 times / day·Bits, while total Dose(TID) is greater than 100 krad(Si).