Study On Single Event Transient And Hardened Methods Of Field Effect Transistor

As the main working environment to aerospace equipments, space environment is full of various energetic particles. Ionization effect will be induced when a energetic particle strikes through semiconductor devices in aerospace equipment. And then single event transient effect may be caused in these semiconductor devices even in the system which is made up by these semiconductor devices. Aerospace equipment may loses its function or be damaged. Semiconductor industry has already entered mature nanometer era. Single event transient effect have more and more significant influence on aerospace equipments because the feature size continues to decrease, threshold voltage is down and space between semiconductor devices is shortened. So study on mitigating the influence of single event transient effect and radiation hardened by design is necessary. Based on the situation above, influences to single event transient effect of field effect transistors with different hardened methods are studied.In this paper, mechanism of action for single event transient effect to individual field effect transistor is studied. Based on theoretical derivation and technology computer-aided design, the basic characteristics and single event transient effect under different ion-incidents are studied by various numerical simulations. Meanwhile, with the simulation results and structural innovation, different hardened methods to mitigate single event effect are presented. In order to ensure their basic characteristics and effectiveness of mitigating single event transient effect, different measuring methods are employed. The main points and results presented in this paper are shown as follows:1. Conventional field effect transistor and the classical guard-drain hardened method with 45 nm feature size under different ion-incidents are numerical simulated with both single-device and mixed-mode by using three-dimensional technology computer-aided design. Single event transient effects of conventional field effect transistor and the classical guard-drain hardened method in both single semiconductor device level and circuit level are presented. And the simulation results shows that electric field from the additional electrodes of guard-drain via 45 nm process have a strongly influence to drain, guard-drain hardened method is ineffective to mitigate single event transient effect with feature size of 45 nm or smaller.2. Based on 45 nm feature size and extension of guard-drain hardened method, a novel hardened method called drain-wall is proposed. The three dimensional numerical simulations about single-device and mixed-mode within different ion-incidents show that electric field from the additional electrodes of drain-wall have no effect on drain, and this ensures that hardened field effect transistor can work properly. Moreover, the additional electrodes can effectively mitigate the influence from single event transient effect.3 Three dimensional numerical model for source/drain on insulator hardened method via 45 nm feature size is built. According to the analysis of the data of both single-device and mixed-mode numerical simulations, source/drain on insulator is proven as an effective technique to mitigate single event transient effect. Meanwhile, thermal issue in silicon on insulator and the problem of that the drain-wall hardened method can only work for N-type field effect transistor are solved by using such a hardened method.