Precise Model And Parameter Extraction Research In Sub-nanometer CMOS Technology Parasitic Effect And Its Variation

With the feature size of CMOS technology scaling down to sub-nanometer process, the shrink in size of device, contact and interconnect lead to continual enlargement of their parasitic capacitance and resistance. The sub-nanometer process parasitic effect has more and more serious influence on performance of devices and circuits. The delay produced by process parasitic effect exceeds the device’s intrinsic delay, meanwhile, process parasitic effect bring huge challenges in high-speed circuits design such as timing analysis, power analysis and signal integrity. As a result, accurate description and modeling of process parasitic effect variation for designers in circuit simulation is very significant.This thesis focuses on research of process parasitic effect variation in sub-nanometer CMOS process. The research intends to analyze deeply and develop MOSFET gate-around parasitic capacitance model, poly-silicon resistor model in front-end process and the variation-aware parasitic parameter extraction in back-end interconnect process. This research designs and fabricates capacitance and resistance test structures independently using sub-nanometer CMOS technology. Based on silicon data, this research develops modeling and extraction flow to optimize traditional SPICE model and interconnect technology format (ITF).Based on such target mentioned above, this thesis work can be summarized four parts:1. For extrinsic gate-around capacitance of MOSFET, this thesis focuses on influence of contact to poly space (CPS) and contact to contact space (CCS) variation on the gate to source/drain fringing capacitance (Cf) in 40nm technology. The work designs Gate-poly test structures and Field-ploy de-embedding structures respectively in 25 CPS and CCS dimensions. Through the analysis of silicon data from the fabricated test structures above mentioned, Cf has obvious variation in different layout design. In some CPS and CCS which is the smallest size in design rule, the variation of Cf is nearly 200%. This thesis develops layout-dependent effect SPICE model based on silicon data. Cf fitting error with silicon data is under 5% and the model is under verification accurately.2. For poly-silicon resistor, this thesis proposes modeling topological structure, and focuses on poly silicon resistor’s non-linear effect’s models which contain temperature and bias voltage characteristics using 40nm technology. Based on the silicon data of 42 dimensions N+/P+ poly-silicon test structures, Temperature-Dependent Characteristics (TDC)、Temperature-Dependent Voltage Characteristics (TDVC) and parasitic capacitance between poly and substrate are modeled and extracted accurately in the work.3. For muti-layer interconnect technology, this thesis focuses on influence of process effect such as CMP or OPC on parasitic effect. This thesis independently designs one type of on-wafer test circuit, three types of modeling test structure using 55nm 1P4M technology. The on-wafer test circuit is a small capacitance measurement circuit which contains CIEF CBCM (Charge-injection-induced Error-free Charge-based Capacitance Measurement) driven by non-overlapping signal. The test circuit can de-embed system parasitic so the accuracy of test circuit can reach to 0.01fF level, and area of capacitance DUT can be decreased by 1/160 compared with traditional large capacitance test structure. Modeling test structures and calibration structures contain coupling capacitance test structures in different width and space, area capacitance test structures in different width and space, overlap capacitance calibration structures in different width and space and Kelvin resistance test structures in different width and space.4. For muti-layer interconnect technology, different from the SPICE modeling method in device parasitic effect, this thesis use LPE tool to establish the interconnect layout parasitic extraction flow. Based on this flow, typical ITF reflected local variation and corner ITF reflected global variation have been optimized to modeling the interconnect process parasitic effect. In procedure of calibrating the typical ITF, extraction error is very evident from the basic typical ITF given by foundry without any process variation compared with silicon data. The extraction error of coupling capacitance is almost over 20%, the largest error is 60%. The extraction error of area capacitance is generally in 5%～15%. The extraction error of resistance is basically in 20-50%. To decrease the extraction error of typical ITF, this thesis develops an optimization flow of typical ITF which includes strategy of modification in interconnect and dielectric dimension based on silicon data. And after the flow, the optimized typical ITF extraction error with all test structures is under 5%. In procedure of calibrating the corner ITF,3a of interconnect and dielectric is correct to make the silicon data located in range of extraction data. The extraction accuracy and range of optimized typical ITF and corner ITF in this thesis all meet industry standards.Based on state owned sub-nanometer platform, this thesis work has developed and optimized sub-nanometer CMOS process parasitic effect variation model and extraction flow. The highlighted achievements are as follows:1. Test structures and de-embedding structures of Cf using 40nm CMOS technology has been designed independently and layout-dependent effect of Cf has been proposed creatively. The corresponding model and extraction flow has been also developed to estimate influence of layout-dependent effect on devices. The achievements are published in Solid-State Electronics which is retrieved by SCI.2. Modeling flow of temperature and voltage bias characteristics in 40nm technology are established to describe non-linear effect of poly-silicon resistors. The SPICE model which are developed can estimate influence of poly-silicon in circuit simulation accurately. The achievements are published in International Conference on Engineering Technology and Application which is retrieved by El.3. Interconnect parasitic test circuits and test structures using 55nm CMOS technology have been designed independently. Based on silicon data, extraction flow and modification strategy have been developed to optimize typical ITF and corner ITF. This work not only afford ITF which can meet industry standards, but also have instruction significance of parameter adjustment in back-end process and place& route in circuit design. The achievements are published in IEEE Electron Devices Letters which is retrieved by SCI.