| Relentless technology scaling has helped us improve VLSI performance by over five orders of magnitude and significantly lowering cost. As the dimensions shrink, we are adversely affected by process variations. To keep track of process parameters, the wafer fabrication facility adds test structures on the scribe lines to measure the various electrical parameters. There about 15 sets of these structures provided around the wafer. Ad hoc instruments are used to collect this parametric data. A typical 4mm by 4mm die size in a 65 nanometer process on a 300mm wafer can have approximately 4000 individual die's per wafer. The parametric data collected on just 15 sites does not provide us with enough granularity of data to understand Lot to Lot, Wafer to Wafer or Die to Die variations. In this research we analyze the data collected on test structures built in to every individual die. The test structures being Ring oscillator with no loading, Ring oscillator in different orientation, Ring oscillators with different metal layer loadings, via resistance structures, Metal layer resistance structures and multi sized transistors. High speed Automatic Test Equipment is used to collect the data. The research is focused mainly on the variation data and not on the absolute value of the collected parameters. The goal of this research is to quantify the variation only and hence all data is normalized. |
