The Research Of Parasitic Effect And Model In 40nm MEOL CMOS Process Technology

With the technology node scaling into sub-nanometer,the layout parameter and geometry have decreased and lead to parasitic effects.The influence is becoming stronger.Meanwhile,the impact of process variation on devices cannot be ignored.Thus,building an accurate MOSFET model can improve the precision for RF circuit simulation.Based on model,PDK(Process Design Kit)combines the full-custom design and process technology.It can reduce the cost via forming a design platform with simulation and verification programs.The research divides the parasitic capacitance around the gate into several components.The range of electric lines in each capacitance is identified,as well as category.The research also studies process variations,such as random dopant fluctuation,LER/LWR(line edge roughness/line width roughness)and OTV(oxide thickness variation).Optical proximity effect and its solutions are also introduced.Based on a dual-k perpendicular-plate capacitance,a semi-analytical gate-to-source/drain fringing capacitance model is extracted.The model takes layout coefficients,CCS(Contact-to-Contact Space)and CPS(Contact-to-poly Space),into account.With TEM results,the model also analyzes variations of LER/LWR,OTV and over-etched contact.Majority of the errors between model and silicon data are under 15%and meet industry standard.Parasitic effects not only can be described by device model but also can be displayed in PDK.The research introduces the flow charts for designing PDK and the performance of CDF(Component Description Format)in circuit design.According to the model,we build some SKILL files to describe the RF devices in 40nm technology.The callback functions are adjusted to parameterize geometry and parasitic effects,for instance,well edge-proximity effect.The parameterized cell is built in the end.This paper extracts a gate-to-source/drain fringing capacitance model with layout parameters and build Pcells of RF devices based on 40nm technology.It is beneficial for developing 40nm process in the future.