Research Of Variation-aware IC Interconnects Parasitic Extraction For CMOS Process

As the IC process technology scales into sub-100nm, delay induced by back-end interconnects become larger. It overtakes the delay induce by MOSFET gates and become the main part of circuits delay in Integrated Circuits (IC) and the main course that limits IC’s performance. It is critical to use Layout Parasitic Extraction (LPE) tools to accurately extract interconnects’parasitic resistances and capacitances in aimed IC. Running post-layout simulation with these extracted parasitic RC instances is more and more important.16-inch Wafers are overtaking12-inch wafers to fabricated deep sub-nanometer VLSI. Even larger wafer will be developed. Interconnects layers’number in IC has grown to8-9, even ten. The advanced semi-conductor process is so complicated that the process conditions differ greatly in different wafers or in different dies at the same wafer. These differences may affect the effective unit parasitic parameters of backend interconnect and lead to parasitic parameters’variation. It becomes a very important research topic that how to accurately extract the statistical parasitic instances of backend interconnects, make them be able to describe the influence of semi-conductor backend process variation on interconnects and finally use them in post-layout simulation for ICs.This paper focused on interconnect parasitic parameters extraction on40nm CMOS process technology and try to present a complete method to extract a process variation-aware Interconnect technology Profile. In order to investigate the inter-line parasitic capacitances between metal interconnects in the same layer and intra-layers parasitic capacitances between interconnects in the two neighbor layers, find out the connection between their values and process variation, this paper design five test keys for modeling interconnects:(1).Metal Comb test structures on one single metal layer for parasitic metal inter-line Capacitors measurements and extraction of thickness of metal layers and width loss induced by etch process.(2). Structure composed of comb layout on two neighbor layers cross over each other for the parasitic intra-layer MOM Capacitors measurement and extraction of thickness of every single dielectric layer between two neighbor metal layers as well as its permittivity.(3) Inverter Ring Oscillators (RO) for unit gate delay measurement without any metal RC load;(4).Inverter RO with small parasitic inter-line coupling capacitors loaded between every two inverters. Their results of post-layout simulation after parasitic extractions are able to verify accuracy of extraction rule related to inter-line parasitic capacitances.(5).Inverter RO with small parasitic intra-layer MOM metal capacitors loaded between every two inverters. Their results of post-layout simulation are able to verify accuracy of extraction rule related to intra-layer parasitic capacitances. In this paper,7different kinds of large inter-line coupling capacitors in M1-M7,5kinds of different intra-layer MOM metal capacitors in M1&M2-M6-M7and7kinds of inverter RO circuits are designed and manufactured with40nm dual damascene Copper interconnects process technology.All the above-mentioned test structures are on-wafer scanning measured and statistically analyzed. The measurements data indicate the influence of process variation on parasitic capacitance of interconnects. First, there are large scale fluctuations in parasitic inter-line capacitances and intra-layer capacitances. Secondly, the inter-line coupling capacitances in metal layers made by the same process flow are largely correlated. The interconnects of M2-M7are all fabricated by dual Damascene process, correlation of their inter-line capacitor measured values are all above77%; while inter-line capacitances in metal layers made by different process, for example, Ml fabricated by single Damascene process, have small correlations with inter-line capacitances of M2-M7. Correlations of Ml inter-line capacitor measured values between capacitors’ in other layers are all below50%; Intra-layer capacitances have even smaller correlations because Correlations of all the intra-layer capacitor measured values are all below20%. These conclusions not only offer basis for variation-aware Interconnection Technology Profile (ITP) extraction but also indicate that correlations of interconnects process should be considered while tuning the process parameters in ITP file.The most popular used backend interconnect parasitic RC parameters extraction method is ITP analyzing method. It is the method that defining totally80process parameters such as every single metal layer’s thickness T, every single dielectric layer’s thickness H、permittivity ε、Delta width induce by etch process ΔW、 Minimum interconnects width Wmin in an ITP file. Based on this ITP file, deduce and produce a RC extraction rule file; according to this rule file, finally extract the parasitic resistance and capacitance between each nodes in circuits netlist of a certain integrated circuits by LPE toolkit. In this traditional method only idealized parasitic resistance and capacitance value can be extracted from each node in circuits, it is impossible to simulate and evaluate the variation of parasitic resistance and capacitance generated by the process fluctuations. According to this, this paper optimize the extraction method of typical ITP and corner ITP, creatively present a parasitic capacitance correlation included process variation aware back-end interconnects parasitic parameters extraction method. For the first time, induce capacitance correlation analysis in interconnects parasitic capacitance extraction and embed the optimized extraction flow into the IC design flow. Monte Carlo simulations are cast on different types of Ring Oscillators circuits; the simulation results verify the accuracy of parasitic extraction method.3D structures of the first kind and second kind of above-mentioned capacitors in are built in Synopsys’s field-effect simulation software Raphael by inputting capacitors’layouts and initial ITP file measured by Transmission electron microscope. Simulations are performed on these structures in random walk method. Based on median value of these parasitic capacitors’measurements data, the typical process parameters value of each metal layer and dielectric layer are extracted and combined into the typical ITP file for this process technology. ITP file can be calibrated and optimized according to the comparison of simulated capacitance values and median measured values of parasitic capacitors. After the calibration, all the difference between simulated and measured capacitance are less than10%. Typical capacitance values are extracted according to extraction rules generated by the typical ITP file. The deviations of extracted values from median value of measurements are all less than10%. Based on typical ITP file, variation-aware ITP file is built according to the parasitic capacitor structures’ statistical measurements. Upon distribution of these capacitors’ value, the correlations between the values of inter-line capacitor in every single metal layer are analyzed by Principle Component Analysis (PCA). Three principle components of M2-M7inter-line coupling parasitic capacitors which have more than98%accumulative contribute rate are calculated based on their measurements’distribution by PCA. The load factors of these three main principle components are calculated, according to which the standard deviation values of inter-line capacitors’values excluded correlation factors are obtained. The standard deviation values can be used to build statistical model of ITP related process parameters. Using rule derived from the optimized40nm variation-aware statistical ITP, post-layout netlists including variation-aware parasitic can be extracted on RO loaded with inter-line capacitors and intra-layer capacitors. Finally, Monte Carlo simulations are performed upon the netlists and the statistical distribution of simulation data is very consistent with the statistical distribution of actual circuits’ measurements. The output signal periods of33stages RO loaded with M1inter-line capacitors mean measured values and Monte Carlo simulated values only have2.54%difference between each other’s and difference between their standard deviations is only3.65%; the two differences number between simulated and measured values of11stages RO loaded with M2inter-line capacitors are-9.16%and9.89%; the two differences number of33stages RO loaded with M1&M2intra-layer capacitors are-1.7%and8.22%. All the Monte Carlo simulated mean value and standard deviation of RO verification ciruits’signal periods have less than10%differences compared to their measured data. It is qualified according to IC industry standard.Based on state-owned40nm process platform, this paper independently establishes and optimizes the40nm CMOS process variation-aware interconnects technology profile extraction method; the outstanding results achieved are as follows:1. Independently, create a set of test structures for the40nm CMOS process interconnects parameters’ extraction. Including the parasitic capacitors for ITP extraction and Ring Oscillators for circuits’ simulation verification.2. Independently optimize the traditional typical ITP file extraction method; present a new complete extraction flow; creatively embed the3D backend parasitic simulations and the RC extraction toolkits’calibration by parasitic capacitors measurements into ITP extraction flow. The accuracy of process parameters in typical ITP file is highly improved. 3. Upon distribution of parasitic capacitors’ measurements, the correlations between the values of parasitic coupling capacitor in every single metal layer are analyzed by Principle Component Analysis. Extraction method of variation-aware ITP file including the correlation ship of single-layer coupling capacitors related process parameters is presented. The Monte Carlo simulation results of RO circuits’ postlayout extracted netlists quite fit the mesurements statistical data, which is up to the standard of industry.